Quick prototype development of ASICS based on Xilinx FPGA 
 
    With products becoming more and more complex whilst requiring earlier deadlines, shortened simulation and fine-tuning stages with FPGA reprogrammable technology has become a necessity.

Xilinx FPGA, through their advancement in flexibility and results density, permit an emulation of whole or part of an ASIC developed from hardware description languages  such as VHDL or Verilog.

Multi Video Designs brings together all its experience on FPGAs to ensure an optimal use of the latest FPGA technologies such as Virtex-II Pro or Virtex 4, and thereby completes the development of the prototype in the shortest possible time.		    
           
        XilinxVirtexVirtex-II    
             
    Synthesis tools used in this type of operation are CERTIFY or CERTIFY SC (Single Chip) from Synplicity or SYNPLIFY-PRO for some designs. Those tools allow optimised synthesis on Xilinx FPGA targets, of a code firstly developed for ASICs.
Multi Video Designs and Synplicity work together as partners for this ASICs prototype activity.		    
           
        SimplicitySimplify ProCertify    
           
    On request, other synthesis tools can be considered.

Proposed services consist of  :
  • Analysis of feasibility and choice of FPGA model.
  • Analysis  of expected consumption (core and I/Os).
  • Thermic considerations.
  • Choice of FPGA(s) configuration mode, according to requirements.
  • Recommendations about the writing style hierarchy notions, in order to ensure an effective synthesis on the FPGA target. Isolation of code sections that could require specific FPGA's resources  (RAM blocs, DLL, DCM, DDR register…).
  • Choice of pinout (before PCB release), to meet electrical constraints (simultaneous switching of capacitive outputs) and timing constraint.
  • Writing electrical constraints, placement and timing files to meet the specifications.
  • Logical synthesis, partitioning, placement and routing, checking of constraints with respect of configuration files.
  • Suggestions for evolution of the source code to improve density and/or result.
  • Production of VHDL or Verilog files, back-annotated for timing simulation.
  • Application debugging assistance by inserting test points into the design, without recompiling.
  • Use of Xilinx CHIP SCOPE (Integrated Logical Analyzer – ILA).
  • VHDL / Verilog functional or timing simulation.
    
           
    Development stream :    
        Design iterations, Chipscope    
           
    In addition, MVD provides full prototype production, using the latest technologies for routing, PCB design and components selection :
  • Use of high density packages :
  • Chip scale Ball Grid Array 0,8 mm pitch (ex : CS144)
  • BGA 1,27 pitch (ex : BG 432)
  • Fine Pitch Ball Grid Array 1 mm pitch (ex : FG456)
  • Flip Chip Fine Pitch Ball Grid Array (ex : FF896)
    
           
        BG432 package   BG256 package   CS144 package    
        BG432 package    BG256 package    CS144 package    
           
     
  • Impedance matching on PCB tracks :

    On request, printed circuit tracks can be impedance matched, in order to meet data integrity requirements, particularly on high speed connections such as LVDS, SSTL...

    For PCB manufacture and layout, MVD utilise a network of subcontractors, renowned in Europe for leading development within their specialist fields, without compromising completion deadlines.



    For further informations , please contact the following address :

    info@mvd-fpga.com
    edgard.garcia@mvd-fpga.com