High Speed I/Os and fast communication standards
 
    New standards

Up-to-date applications require both data exchanges and communications each time faster. New standards come out steadily, each one fitted to a very accurate domain. MVD developed a deep know-how in order to meet its customers requirements and needs.		 PCI interface 64bit/66MHz
PCI interface 64bit/66MHz		  
           
     I/O configuration

Spartan-II,-III Virtex-E, Virtex-II, Virtex-II Pro, Virtex4 FPGA families have I/Os features making possible ultra-fast interfaces implementation, respecting set up standards and signals integrity. I/Os specific configurations permitting impedance fittings (Digitally Controlled Impedance) are especially used, but also communication standards by differential pairs (LVDS, LVPECL, RocketIO,...), without forgetting DDR functions (Double Data Rate) essential for interfacing with a great number of ultra-fast memory components (SDRAM DDR, ZBT SRAM).		 SDRAM DDR controller
SDRAM DDR controler mode SSTL DCI		  
           
      Those techniques, mostly up-to-date, require deep skills for printed circuits routing. Impedance adaptation of lines is often needed to guarantee signals integrity and control of high density boxes technologies (high density BGA packages, Chip Scale, Flip Chip...). LVDS pairs transmission 200Mbit/s
LVDS pairs transmission 200Mbit/s		  
           
    Implemented standards

MVD has already implemented different high-speed communication standards, as well on FPGA as on electronic boards :
  • PCI bus (32/33 et 64/66) and  Compact PCI.
  • SSTL and HSTL Standards for communication between high-speed circuits.
  • LVDS with or without Data/Clock recovery for communication between systems.
  • LVPECL
  • RocketIO
  • Data transmission through fibre-optic.
optical fiber 160Mbit/s
Data transmission through fibre- optic 160Mbit/s		  
           
    Realizations

Among MVD concrete developments, we can find : 
  • 66/64 PCI interfaces and Compact PCI.
  • SDRAM DDR memory controllers
  • Data translation to LVPECL standard
  • Data translation to cabled pairs in a LVDS mode, with clock/data recovery device developed in FPGA  (MVD developed algorithm  - Data and clock pass through the same cabled pair).
  • 1 Gbits/sec  fibre-optic interfaces
optical fiber 1Gbit/s
1Gbit/s fibre-optic interface		  
           
      For further information, contact us at the following address : info@mvd-fpga.com