Training-course - VHDL logical synthesis and simulation for design with Xilinx FPGAs (reference 002572A)
 
        5-day training-course    
           
        Design methodologies for programmable components were completly changed when VHDL language appeared.

Thus, it represents a major interest for design portability and evolutions.

Logical synthesis can achieve physical implementation of a design. The whole of the synthetisable VHDL is used, which is a sub-set of the VHDL language.
Simulation allows to check the behaviour of a design before or after implementation in the targeted component. It's an important stage that can save time for board testing..		    
           
      Our educational methods will help you to master progressively subtleties of VHDL language, Xilinx FPGAs, combined tools and suited development methodologies.

Development techniques of synchronous digital circuits will be reviewed, in order to get free from usual problems of conception. Those different elements will be implemented from VHDL language.

Many practical experiences will help you to find out progressively language, architectures and compilation tools about growing complexity developments, in ISE Foundation development environment, but also through Synplicity Synplify-Pro synthesis tool and Mentor Graphics ModelSim simulator.		    
           
  Logo ISE-FoundationLogo XSTLogo SYNPLICITYLogo ACTIVE-HDL  
         
    Designing with FPGA

After a short introduction about hardware (HDL)  and FPGAs description languages, basis notions of VHDL language will be set out and put into practice on last generation Xilinx FPGA.

Different elements of synthesisable VHDL language and synthesis mechanisms will be exposed and detailed.  Particular attention will be paid to writing styles permitting to get reliable and predictable synthesis results (means used and running frequency).

Main points to reduce the conception cycle length :

    
    Methodology of synchronous designs developments, and secured control of asynchronisms  when inevitable.

    
    Advised written style in VHDL language for predictable and effective logical synthesis. Optimal control of hierarchy.    
  Synthese  
         
    Spartan-II, Virtex-E and Virtex-II Xilinx FPGA architecture : learn how to increase running frequencies while reducing costs and using in an optimal way specific possibilities (DLL, DCM, DCI and impedance control, RAM blocks used as logical resources...).    
  Logo SPARTAN-II Logo VIRTEX-II  
         
    How to configurate your tools according to your design needs :    
  Configuration outils  
         
    Save time using constraints automatic generation tools such as "Constraint Editor" and  Floorplanner :    
  Constraint EditorFloorplaner  
         
    Check coherence of results achieved thanks to compilation reports :
  • SYNTHESIS report, pointing out logic means used in design
  • MAP report : Apportioning into elements available in FPGA
  • PAR report : Information about place and route algorithms progress
   Rapports compilation
           
    Reduce temporal simulation stages, using "Timing Analyzer" and its " Cross Probing " possibilities with floorplanner and synthesis tool.   Analysis report
           
    Control weak sections of your design through " FPGA Editor " and add internal test points to FPGA without recompiling.   FPGA Editor
         
    Save time in functional and/or temporal simulation, using  both " Testbenches " wizard, delivered with Foundation ISE, and most performant simulators.    
  TestbenchTimings  
         
    Reduce adjustment time taking advantage of JTAG configuration and "ChipScope ILA" (Integrated Logic Analyzer) option.
  
         
    Synthesis

You learn syntax and set of instructions used in VHDL synthesis.
           
      Through high performance tools and real examples, you will meet advantages and limits of different writing styles.   VHDL
           
Travaux pratiques       Many practical works will permit you to acquire methodology and rigor necessary to carry out complex and performing designs.  
           
      You will exploit synthesis reports and graphic tools in order to control and improve quality of your design.    Rapports synthese
           
      Among the approach subjects :

  • VHDL language syntax
  • Operators
  • Usable type of data in logical synthesis
  • Concurrent instructions set
  • Sequential instructions set
  • Styles of writing recommended for an effective synthesis
  • Management of the hierarchy
  • Predefined attributes of the language
  • Genericity
  • Call of specific primitives for a technological target
   
             
    Simulation

You will use unsynthesisable set of instructions in order to take advantage of VHDL language best possibilities during simulation.
           
      Testbench will permit you to apply stimuli to your design as to model behavior of your board components.   Testbench
           
      During this phase, the complementary instructions set, usable in modeling and simulation will be analysed, and put into practice.

In particular :

  • Functions and procedures
  • Packages and libraries
  • Types of objects usable in simulation (file, time, record...)
  • Extended instructions set usable in simulation
  • Signals value nitialisation during the declaration
  • Use of ASCII files of test patterns
    
             
Gestion fichiers VHDL       You will use VHDL language files (writing and reading) in order to make high level scripts and simulation reports.  
           
      Graphic tools will help you to control your design behavior.   Outils graphiques VHDL
           
    Tools

Tools used during training-courses are among the most performant in the market :
  • Synthesis :
    • Synplify (Synplicity)
    • FPGA Express (Synopsys)
    • Foundation ISE (Xilinx)
    • Leonardo Spectrum (Exemplar)
  • Simulation :
    • Active-HDL (Aldec)
    • ModelSim (Model Technology)

However, practical work can be performed with other tools. In that case, please contact us before.

    
           
    Documentation

Technical manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards.
  • Architectures and Xilinx tools manual
  • Training manual " VHDL, simply "
  • Training manual " Simulation and modeling in VHDL language "
    
           
    Trainers

Our trainers are all experienced designers, conceiving electronic systems using FPGA. So, you can benefit from their designers' experience.		    
           
    Guarantee

Multi Video Designs provides free technical help (by phone, fax or e-mail) to each participant after the training.		    
           
    Hardware configuration recommended
  • PC Pentium III 800 with the folowing configuration :
    ( 1 PC for 2 participants )
    • 256 Moctets of RAM
    • Windows 2000 or XP
    • 600 Moctets free on the harddrive for software installation
  • Video-projector and white-board
    
           
    Other trainings :

If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation