Training - PowerPC MPC7400/7410 (reference 002586A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • Practical exercices are built with Diab Data compiler, downloaded on a 7400 target board through the EST probe
  • VisionClick debugger is used to control code execution
    
           
    Related Trainings
    
           
    Prerequisites
  • Experience of a 32 bit processor or DSP is mandatory
    
             
  Course Objectives
  • Optimized code writing based on pipeline knowledge
  • Alignment rules are to be determined to avoid cache replacement of data being processed
  • Data flows between SDRAM, L1 caches and L2 cache are highlighted
  • Cache coherency protocol is introduced in increasing depth
  • Vector instructions and new C operators are viewed in detail
  • Data streams parametring is emphasized through an example
  • This course covers bus operation, either 60X or MPX mode
  • Through a FFT algorithm, the instructor shows how to vectorize processing and reduce execution time using data streaming
  • The internal performance monitor has been programmed so that different versions of the FFT algorithm implementation can be compared
    
           
    Duration
  • 5-day course
    
           
    Topics

(The full description of this course can be provided on request)

MPC7400/10 PIPELINE

  • Superscalar out-of-order execution
  • Branch Target Instruction Cache
  • Static vs dynamic branch prediction
  • Coding guidelines

L1 AND L2 CACHES

  • Cache basics
  • PLRU L1 replacement algorithm, FIFO L2 replacement algorithm
  • Hardware data cache flush
  • Cache coherency based on snooping, the MEI, MESI and MERSI state machines

INTERNAL DATA FLOWS

  • Data and instructions queuing mechanism to decouple bus operation and internal activity
  • The Memory Sub System
  • The load fold queue and the store miss merging

MPC7400/10 SPECIFIC UNITS

  • Power management
  • Performance monitor
  • JTAG debugger
  • Differences between 7400 and 7410

THE UISA LAYER

  • Cache related instructions
  • Little-endian emulation
  • PowerPC timers

ALTIVEC IMPLEMENTATION

  • Altivec registers
  • Vector load / store instructions
  • Vector integer instructions
  • Vector float instructions
  • Vector permut instructions
  • ANSI C extensions to support vectors
  • Altivec implementation on 7400/10
  • Data streams

THE OEA LAYER - MMU

  • MMU goals
  • Process protection
  • Tablesearch, hash value
  • MMU implementation in real-time sensitive applications

THE OEA LAYER - EXCEPTION MECHANISM

  • Supervisor registers
  • Context saving through SRR0/SRR1 registers
  • Handler table
  • Exception nesting

MPC7400 HARDWARE IMPLEMENTATION

  • Auto-check on power up
  • Bus features : address pipelining, split transactions
  • 60X bus cycles
  • MPX data only transactions
  • Synchronous SRAM technologies
  • L2 bus interface
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
    Other trainings :

If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation