Training - PowerPC MPC825X/6X/7X/8X hardware implementation (PowerQUICC II) (reference 002589A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • This training course is approved by Freescale
    
           
    Related Trainings
  • The MPC826X software training covers all software related (reference 002588A)
  • The PCI training (reference 002596A) is recommended for designers using the PCI interface
  • Only a few points are shared by both MP826X courses
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
    
           
    Prerequisites
  • Experience of a digital bus is recommanded
    
           
  Course Objectives
  • This course describes the 60X and local bus operation
  • Data flows between L1, L2 and SDRAM are viewed in detail
  • An SDRAM introduction shows the page management in multiple-bank SDRAM
  • The PCI interface is viewed in detail
  • The course explains how to find GPCM, UPM or SDRAM machine timing parameters from timing diagrams
    
           
    Duration
  • 2-day course
    
           
    Topics

(The full description of this course can be provided on request)

MPC826X INTRODUCTION

  • Enhancements compared to MPC86X
  • Block diagram : characteristics of each of the 3 internal modules PPC603ev core, SIU and CPM
  • Bus traffic distribution between local bus and 60X bus
  • HIP7 device packages

CLOCKS AND RESET

  • Internal clocks description
  • PLL multiplication factor determination through MODCK inputs and configuration word
  • Clocking of the MPC827X/8X
  • Reset sequence
  • Configuration word acquisition process

THE 60X BUS

  • Pinout
  • External address latch and mux requirement when the 60X bus operates in multimaster mode
  • Bus features : address pipelining, split transactions
  • 60X bus mode : address phase and data phase
  • Dynamic bus sizing : connection of 8, 16 or 32-bit peripherals

CACHE COHERENCY IN MULTIMASTER APPLICATIONS

  • Bus interface unit : the decoupling buffers
  • Cache coherency in multimaster applications
  • MEI state machine
  • Snooper initiated transactions when a clean, flush or kill broadcast is received

THE MPC2605 L2 CACHE

  • MPC2605 L2 cache introduction
  • Cast-out cycles when L2 cache operates in copyback mode
  • Hardware interface, timing diagrams

THE MEMORY CONTROLLER

  • Arbitration between internal and external masters
  • The 60X to Local bus bridge
  • UPM implementation
  • GPCM implementation
  • SDRAMs machine description
  • Bank vs page interleaving

THE PCI BRIDGE

  • Arbitration
  • Definition of inbound and outbound address ranges
  • Bus errors processing
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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