INTRODUCTION TO 405

• Architecture of a 405-based System-on-Chip
• Programming model, the 4 register groups GPRs, SPRs, DCRs and memory mapped

THE CORE ARCHITECTURE

• 5-stage pipeline operation
• Instructions flows through the pipeline
• Speculative execution, guarded memory, SGR register
• Serialization : prefetch barrier implementation by means of unconditional branch instructions, isync instruction
• Cache basics : organization, replacement algorithm, write policies
• Data flow between external memory and caches
• Cache programming interface
• Memory Management Unit : memory attributes definition (cache enabled / cache inhibited, copyback / writethrough)
• Translation Lookaside Buffer initialisation
• Parity control for caches and UTLB
• Cache control and debugging features
• Load / store buffer, sync instruction

PowerPC ARCHITECTURE FOR EMBEDDED APPLICATIONS

• Branch instructions
• System call instruction
• Load / store instructions
• Semaphore management with lwarx / stwcx. Instructions
• Arithmetical and logical instructions
• The PowerPC EABI
• Cache related instructions
• 16-bit mac instructions
• Exception processing
• Critical versus non critical interrupts
• Syndrome registers updating when an exception is taken
• Core timers : PIT, FIT and WDT
• Reset

INTEGRATED DEBUG FACILITIES

• JTAG debug
• Logic analyser connection through Mictor connectors
• The 405 instruction trace port
• Hardware vs software breakpoints

HARDWARE IMPLEMENTATION OF THE PPC405 CORE

• External connections
• Clock and power management interface
• CPU control interface
• Reset interface
• External interrupt controller interface
• The OCM busses
• Instruction-side local bus interface
• Data-side local bus interface
• DCR interface

APU CONTROLLER