• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This comprehensive course provides students with an introduction to designing with Xilinx FPGAs using the ISE Series software tools. This course covers ISE 5 features such as Architecture Wizard and the Pin and Area Constraint Editor (PACE). Other topics include design planning, implementation options, and global timing constraints.

• For more emphasis on improving overall design performance, take the follow-up course Design for performance, ISE5 (ref. 002833A) , which builds on the basic principles covered in this course.

• Working knowledge of HDL (VHDL or Verilog)
• New to Xilinx FPGAs

• Learn how to use ISE Series software quickly and reduce design time

After completing this training, you will be able to:

• Implement an FPGA design with the Xilinx Project Navigator
• Use Architecture Wizard to create DCM instantiations
• Use the PACE tool to assign pin locations
• Read reports to determine whether design goals were met
• Assign pin locations and enter basic global timing constraints using the Constraints Editor
• Locate and modify the implementation options

• 1-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

• Introduction
• Basic Virtex-II Architecture
• Xilinx Design Flow
• Architecture Wizard and PACE
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Global Timing Constraints
• Lab 2: Global Timing Constraints
• Implementation Options
• Lab 3: Implementation Options
• Synchronous Design Techniques
• Summary

LAB DESCRIPTIONS

• Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and utilize the Architecture Wizard and PACE tool in the design process. Implement a design using default software options.
• Lab 2 - Global Timing Constraints: Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place and Route Static Timing Report to determine the delay of the longest-constrained path for each timing constraint.
• Lab 3 - Implementation Options: Adjust process properties and I/O configuration options to improve design performance.