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| Training - Designing for performance, ISE
(reference 002833A) |
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Partners
- Do not hesitate to request the detailed course
description by contacting training@mvd-fpga.com
- This training course is approved by Xilinx
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Course description
- Learn design techniques to help improve your
design's performance. Topics include: FPGA design
techniques, HDL coding techniques, the CORE
Generator™ System, power estimation, timing
analysis, advanced timing constraints, and
advanced implementation options. Five labs are
included.
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Prerequisites
- Basic HDL knowledge (VHDL or Verilog)
- Knowledge of Virtex-II architecture, software
tool flow and global timing constraints
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Course Objectives
- Learn effective techniques to improve your
design's performance
After completing this training, you will be able to:
- Write HDL code to efficiently target Virtex-II
architectural resources
- Make path-specific timing constraints using the
Xilinx Constraints Editor
- Improve design performance and manage software
runtime by using MPPR and re-entrant routing
- Create customized cores using the CORE
Generator™ System
- Address board-level issues such as ground bounce
and power consumption
- Run a behavioral simulation on an FPGA design
that includes cores
- Improve design performance by duplicating
flip-flops and pipelining
- Analyze design performance via timing reports and
determine the steps necessary to achieve timing
closure
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Duration
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Topics (The full description of this course can be
provided on request)
TRAINING OUTLINE
Day 1
- Review from Fundamentals Course
- Advanced Virtex™-II Architecture
- FPGA Design Techniques
- HDL Coding Style
- Lab 1: Coding Style
- Synthesis Techniques
- Lab 2: Synthesis Techniques
- CORE Generator System
- Lab 3: CORE Generator System
Day 2
- XPower
- Lab 4: Review of Global Timing Constraints
- Achieving Timing Closure
- Timing Groups and OFFSET Constraints
- Path-Specific Timing Constraints
- Lab 5: Achieving Timing Closure
- Advanced Implementation Options
- Course Summary
LAB DESCRIPTIONS
- Lab 1 - Coding Style: Review code and
analyze its behavior. Look for a better way of
writing code to improve performance and increase
reliability.
- Lab 2 - Synthesis Techniques: Experiment
with different synthesis options and view the
results. Six versions of this lab are available:
VHDL or Verilog language, Synplicity's Synplify
Pro, Mentor's LeonardoSpectrum, or Xilinx XST
synthesis tools.
- Lab 3 - CORE Generator System: Create a
core, instantiate the core into VHDL or Verilog
source code, and run behavioral simulation.
- Lab 4 - Xilinx Review of Global Timing
Constraints: This lab is a quick review of
using the Constraints Editor, and introduces the
lab design that is used throughout the course.
Gets you into the software quickly.
- Lab 5 - Achieving Timing Closure: Review
timing reports and enter path-specific timing
constraints to meet performance goals.
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Documentation
Training manuals will be given to participants during
training. Precise and easy of use, those notes can be
used as a reference afterwards. |
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