• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This course focuses on providing ASIC designers with an FPGA design methodology for improving design performance. ASIC design and verification techniques are compared and contrasted to FPGA design and verification techniques. HDL inference of FPGA resources and coding examples are provided. Advanced techniques using the Xilinx implementation tools are also discussed. The course highlights the Virtex™-II family though most concepts can also be applied to Virtex-based designs. HDL inference of FPGA resources and coding examples are provided.

• A basic background in digital design
• Knowledge of Virtex-II architecture, software tool flow, and global timing constraints
• Intermediate knowledge of VHDL or Verilog
• ASIC design experience

• For ASIC digital designers who want to get the most out of their FPGA design
• Decrease time spent re-targeting ASIC code for Xilinx with a 10-step conversion guide
• Increase performance of the design through code optimization
• Decrease time to market through a higher knowledge of the FPGA design f low
• Improve performance and decrease run-times by using appropriate constraints, implementation options, and implementation tools

After completing this training, you will be able to :

• Write HDL code to efficiently target Virtex-II architectural resources
• Make path-specific timing constraints using the Xilinx Constraints Editor
• Improve design performance and manage software runtime by using MPPR and re-entrant routing
• Contrast the ASIC design and verification flow to the FPGA design and verification flow
• Create customized cores using the CORE Generator™ System
• Run a behavioral simulation on an FPGA design that include cores
• Determine whether design goals were met by reading reports
• Re-target ASIC HDL for a Xilinx FPGA
• Address board-level issues such as ground bounce and power consumption
• Describe and use Xilinx implementation

• 3-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

Day 1

• Course Introduction / Agenda
• Review from Fundamentals Course
• Advanced Virtex-II Architecture
• FPGA vs ASIC Design Flow
• ASIC to FPGA Coding Conversion
• Lab #1: Three-State Multiplexers
• Synthesis Techniques
• Lab #2: HDL Coding Style and Synthesis

Day 2

• Help Resources
• CORE Generator™ System
• Lab #3: CORE Generator™ System
• Behavioral Simulation
• Lab #4: Behavioral Simulation
• FPGA and ASIC Technology Comparison
• Lab #5: Finite State Machine
• Lab #6: Pipelining
• Introduction to the Timing Analyzer
• Timing Groups and OFFSET Constraints
• Path-Specific Timing Constraints
• Lab #7: Advanced Timing Constraints

Day 3