• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This course introduces the Xilinx design flow for implementing DSP functions. Although the main focus of this course is on the System Generator for DSP, this class also includes information on HDL design flow, the CORE Generator™, design implementation tools, and hardware verification. Students will become familiar with the Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware verification.

WHO SHOULD ATTEND ?

• System Engineers and Designers wanting to understand how to implement a DSP design without being expert FPGA designers. Designers will learn how certain decisions made up front will impact the resulting implementation for a given algorithm. This course will also be beneficial to the experienced hardware engineer faced with the task of implementing unfamiliar DSP algorithms.

• For more emphasis on improving overall design performance, take the follow-up course Designing for performance, ISE (ref. 002833A), which builds on the basic principles covered in this course.

• Three FPGA design flows will be presented with a large focus on the Xilinx System Generator for DSP. Tips and tricks will be provided for those flows, but students will be expected to know the fundamentals of MATLAB/Simulink and Xilinx FPGAs
• Although the course includes very basic revision of some DSP algorithms, students should understand the basics of digital signal processing theory for functions such as FIR (Finite Impulse Response), oscillators and Mixers, and FFT (Fast Fourier Transform) algorithm

• Decrease time to market through a higher knowledge of the FPGA design f low
• Increase productivity through practical knowledge of common FPGA design flows
• Learn how to implement a DSP design without having to be an FPGA expert
• Learn how to gain access to high-performance IP libraries
• Learn how to make cost/performance tradeoffs early in the design process and use bit and cycle-true simulations in Simulink

After completing this training, you will be able to :

• Understand the strengths and weaknesses of three design flows (HDL, CORE Generator, System Generator)
• Make a decision regarding which design flow is more appropriate based on needs and FPGA expertise
• Understand the impact of some decisions made in the Simulink environment on the resulting size of the FPGA design
• Debug and optimize a design in the Simulink environment
• Implement a design from start to finish using the System Generator
• Use advanced features of the System Generator
• Run some hardware verification with the Nallatech Demo board
• Appreciate the DSP capabilities of the Xilinx FPGA thanks to real life design examples

• 3-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

Day 1 Implementation Tools

• Introduction
• FPGA Design Flows
• Lab 1: Creating a 12x8 MAC using VHDL
• Lab 2: Creating a 12x8 MAC using the Xilinx CORE Generator for DSP
• Lab 3: Understanding the Basics of System Generator through the Construction of a MAC
• System Generator: Looking Under the Hood
• Lab 4: Looking Under the Hood
• Lab 5: Padding and Unpadding Data

Day 2 Digital Signal Processing Functions

• System Generator: Controlling the System
• Lab 6: Controlling the System
• System Generator: Multirate Systems
• Lab 7: Creating a MAC FIR Using the System Generator
• Lab 8: Implementing a MAC based FIR
• Hardware Verification

Day 3 Digital Signal Processing Functions