| |
| Training - ARM 7/9 system design
(reference 002879A) |
|
| |
| |
|
 |
|
Partners
- Do not hesitate to request the detailed
course description by contacting training@mvd-fpga.com
- This training course is approved by ARM
|
|
|
 |
|
|
|
|
|
|
| |
|
|
|
Practical labs
- For on-site courses, labs can be run
under 3 possible environments :
- CodeWarrior/ADS/AXD
- Eclipse/RVDS
- GNU/Lauterbach simulator
- For open courses, labs are run under Eclipse/RVDS
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
Prerequisites
- A basic
understanding of microprocessors and
microcontrollers
- A basic
understanding of digital logic or
hardware / ASIC design issues would be
useful but not essential
- A basic
understanding of assembler or C
programming would be useful but not
essential
- A basic awareness
of the ARM is useful but not essential
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
Course Objectives
- This course takes
an in depth look at the considerations
you will need to take into account when
designing a system containing either an
ARM7TDMI family or ARM9TDMI family
processor core. Some information on the
latest generation of ARM processor cores,
such as the ARM9E-S family is also
included.
- It is aimed at:-
- Software
engineers who not only want to
obtain details of how to write
software to run on the ARM, but
also wish to obtain an
understanding of hardware design
issues
- Hardware
engineers who need to understand
how to design ARM based systems,
but also wish to obtain an
understanding of the issues of
writing software to run on that
system
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Duration
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
Topics (The full description of this course
can be provided on request)
First day
THE ARM ARCHITECTURE
- ARM operation modes
- The ARM registers set
- Program Status Registers
- Exception handling
- Instruction sets
ARM PROCESSOR CORE
- ARM7TDMI core signals
- The ARM7TDMI instruction pipeline
- ARM7TDMI memory interface
- ARM9TDMI datapaths
- ARM9TDMI pipeline
Second day
ARM AND THUMB INSTRUCTION SETS
- Conditional execution and flags
- Branch instructions
- Single register data transfer
- Block data transfer
- Stack management
- Register access in Thumb
- ARM architecture V5TE new instructions
ARM / THUMB INTERWORKING
- Branch exchange example
- Mixing ARM and Thumb subroutines
- ARM to thumb veneer
- Thumb-to-ARM veneer
- Interworking calls
EXCEPTION HANDLING
- Exception priority
- Vector table instructions
- Chaining exception handlers
- Register usage in exception handlers
- Example C interrupt handler
- Software managed interrupt controller
- Issues when reenabling interrupts
- Invoking SWIs
- Data abort with memory management
Third day
COMPILER HINTS AND TIPS
- Automatic optimization
- Instruction scheduling
- Tail-call optimization
- Loop termination
- Inline assembler
- Stack usage
- Global data layout
INITIALIZING CACHED PROCESSORS
- Cache basics
- Cache flushing
- Write buffer
- Memory management
- TLB and translation tables
- Memory protection, MPU configuration
steps
- System control coprocessor
- Tightly coupled memory
EMBEDDED SOFWARE DEVELOPMENT
- ROM/RAM remapping
- Exception vector table
- Reset handler
- C library initialization
- Scatterloading
- Linker placement rules
- Long branch veneers
- C library functionality
- Placing the stack and heap
Fourth day
AMBA BUS ARCHITECTURE
- AHB Protocol
- AHB Connection Architectures
- AHB Workbook
ARM DEBUG SOLUTIONS
- Debugging with multiICE
- Watchpoints, hardware breakpoints,
software breakpoints
- Semihosting
- EmbeddedICE-RTT logic
- Instruction trace, data trace
- Trace capture
|
|
|
|
|
|
|
|
|
|
| |
|
|
|
Documentation
Training manuals will be given to participants
during training. Precise and easy of use, those
notes can be used as a reference afterwards. |
|
|
|
|
|
|
|
|
|