INTRODUCTION TO THE MPC8560

• Implementation examples
• Internal data flows, OCEAN switch fabric, packet reordering
• Address map, ATMU
• Local vs external address spaces, inbound and outbound address decoding
• Accessing CCSR memory from external master

MAIN FEATURES OF THE e500 CORE

• The L1 caches, PLRU replacement algorithm, 8-way set associativity
• Cache coherency : MEI vs MESI state machine
• Level 2 cache, partition into 128-kb L2 cache plus 128-kb SRAM
• Allocation of data transferred by external masters into the cache
• e500 coherency module
• The Core Complex Bus : high speed on-chip local bus with data tagging
• Exception handling
• JTAG emulation, real time trace when the e500 core executes cached instructions

RESET, CLOCKING AND INITIALIZATION

• Platform clock
• RapidIO transmit clock source selection
• Power-on reset sequence, use of the I2C interface to access serial ROM
• Power-on reset configuration
• Boot page translation

THE DDR-SDRAM CONTROLLER

• DDR-SDRAM operation : a 128-Mbits DDR-SDRAM from Micron is used as an example
• Jedec specification basics, mode register initialization, bank selection and precharge
• Command truth table
• Bank activation, read, write and precharge timing diagrams, page mode
• DDR-SDRAM controller introduction
• Initial configuration following Power-on-Reset
• Address decode
• Timing parameters programming
• Initialization routine

LOCAL BUS CONTROLLER

• Multiplexed 32-bit address and data transfers
• Burst support
• Dynamic bus sizing
• GPCM, UPMs and SDR SDRAM states machines

RapidIO INTERFACE UNIT

• 8-pin parallel interface, LVDS signalling
• Packet pacing support at the physical layer
• Atomic operations
• RapidIO compliant message unit

PCI/PCI-X FUNCTIONAL UNITS

• Data flows : Read prefetch and write posting FIFOs
• Inbound transactions handling, outbound transactions handling in both modes
• Support of multiple split transactions in PCI-X mode
• PCI-to-memory and memory-to-PCI streaming

HARDWARE IMPLEMENTATION OF COMMUNICATION