Training - eTPU programming (reference 003199A)
 
    Partners
  • This training is a combination of our previous eTPU course and the eTPU course offered by Freescale/ASH WARE
  • This training course has been approved by Freescale
  • Practical exercises are developed using the Byte Craft C compiler and debugged using both the ASH WARE eTPU Simulator and the LAUTERBACH multi-core debugger
   
           
    Related trainings
  • Every course that covers a Freescale MCU integrating a (e)TPU details only the particular Host interface, not the TPU microcoding (MPC5XX course 002591A and MPC555X course 003151A)
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
   
           
    Prerequisites
  • Basic knowledge of microprocessor architecture, hardware timers and the C programming language
   
             
  Course Objectives
  • Learn how to solve complex timing problems using the eTPU
  • Learn how to program the eTPU in "C"
  • Learn the channel hardware and how it can be used in a variety of timing applications
  • Learn the programming framework with an emphasis on eTPU-specific issues such as the Event Vector table and function variables
  • Use the Byte Craft compiler to automatically generate information about the build (e.g., header files) used by the host-side CPU code
  • Use the ASH WARE eTPU Stand-Alone Simulator to debug eTPU code
  • Use the LAUTERBACH debugger to verify functionality on target hardware
  • Utilize instruction set, registers, parallelism, and other architectural features to optimally implement timing solutions.
   
           
    Duration
  • 4-day course
   
           
    Topics

Day 1

Tools Installation and Introduction [1.5 hours]

  • Step-by-step installation of Byte Craft's eTPU Compiler.
  • Step-by-step installation of ASH WARE's eTPU Stand-Alone Simulator.
  • Brief tour of Compiler including compiling, project files, multi-file builds, and library directory.
  • Student will modify some eTPU code to perform a calculation, compile, load into simulator and verify calculation.

RAM Host Interface [1 hour]

  • Mapping
  • Reach variables and parameter
  • Host-eTPU registers
  • Memory coherency
  • Exercises on tools
  • Register initialization
  • +MMU/GPIO/Registers
  • local and global variables, etc
  • where to locate them

Channel Hardware Basics [2 hours]

  • A "C-centric" introduction to fundamental channel hardware concepts.
  • Sampling input pin state versus detection of an edge and recording the time at which that edge occurred.
  • Forcing an output pin to a state versus scheduling a output pin edge to occur at a particular future point in time.

Events and Event Handling [ 2 hours]

  • The eTPU is an event servicing device.
  • Using the eTPU compiler to create an event vector table.
  • Examine event and thread response timing diagrams to see where event servicing occurs.

Day 2

Channel Hardware Details [ 2 hours]

  • Step through each of the fields used to program the channel hardware.
  • A step-by-step guide to setting up matches and transition detection.

Microengine [ 1 hour ]

  • Registers presentation
  • Introduction to micro-instructions
  • Initializing a register
  • Data supported (int, frac signed or not ;..;
  • Arithmetic Instructions (+ - / Mac div ....)
  • Exercises

RAM Parameter [1 hour]

  • Mapping
  • The addressing modes
  • Timing
  • Coherency

The Programming Model [ 2.5 hours]

  • Essentially a programmers' model chapter, with emphasis on context and thread issues.
  • Key data type, function variables, explained in detail including memory map. Other miscellaneous issues.

Day 3

Channel Hardware Modes [ 3.5 hours ]

  • Explain details of match/transition and action unit 1/2 using the channel "mode". A problem-solving approach:
  • "How to solve problem X? Use channel mode Y."

Scheduler [2 hours]

  • The round robin scheduler algorithm.
  • Calculating worst case latency.
  • Statistical latency analyses using post processing trace-dump files.

Day 4

Angle Mode [2 hours]

  • Angle mode hardware is a digital phase lock loop (PLL) with a software assist.
  • Underlying concepts and details on the software assist.
  • Basic Tools Issues.
  • Automated testing using the Simulator, including data flow, behavior verification, and code coverage.
  • Auto-code generation in the Compiler solves two-copy problem.
  • Example host-side drivers with auto-code generated from the Compiler.

eTPU Micro-Instruction Overview [1 hour]

  • VLIW machine
  • Instruction format
  • Specific instruction formats

Micro-Engine Programming Model [4 hours]

  • Registers list
  • Execution unit hardware
  • Code condition latch
  • Channel selection
  • Loop
  • Arithmetic instructions
  • Explanation of all possible options
  • Multiply and Mac instructions
  • Practical exercise

Flow Control Instructions [1 hour]

  • Pipeline
  • Branch chart
  • Conditional branches
  • Flush pipe or not
  • Repeat capabilities
  • Call and return instructions
   
           
    Documentation
  • A set of printed course notes is provided that includes the labs at the end of each chapter.
  • A CD is provided that includes course notes, code snippets, labs, and lab answers.
   
           
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