Training - PPC 440 core reference 003528A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • This training course is approved by IBM microelectronics
  • Practical exercices are built with Diab Data compiler, downloaded to a 440EP evaluation board through the Wind River probe
  • Single Step debugger is used to control code execution
  • A full generic CSP [CPU Software Package] developed by MVD is provided to attendees in source code
    
           
    Related Trainings
    
           
    Prerequisites
  • Experience of a 32 bit processor or DSP is mandatory
    
             
  Course Objectives
  • A boot firmware that initializes the MMU has been developped
  • Internal debug facilities are described
  • The course focusses on 440 low level programming, especially the PowerPC EABI
  • Examples of exception handlers are provided
  • A DFT has been developed to explain how to use mac instructions
  • The Floating Point Unit operation is described
    
           
    Duration
  • 3-day course
    
           
    Topics

(The full description of this course can be provided on request)

INTRODUCTION TO 440

  • Internal architecture overview
  • Connection to peripheral IPs
  • Clocking
  • Programming model

THE CORE ARCHITECTURE

  • Pipeline basics
  • 5-stage pipeline operation
  • Speculative execution, guarded memory
  • Cache basics
  • Data flow between external memory and caches
  • Cache programming interface
  • Process vs thread
  • Memory Management Unit
  • Translation Lookaside Buffer initialisation
  • Cache control and debugging features
  • Load / store buffer, speculative loads

BOOK E COMPLIANT CORE

  • Booke E objectives
  • Branch instructions
  • Load / store instructions
  • Semaphore management with lwarx / stwcx. Instructions
  • Arithmetical and logical instructions
  • The PowerPC EABI
  • Cache related instructions
  • 16-bit mac instructions to develop fixed point DSP algorithms
  • Exception processing
  • Syndrome registers updating when an exception is taken
  • Core timers : PIT, FIT and WDT
  • Reset

INTEGRATED DEBUG FACILITIES

  • JTAG emulator use
  • Real time trace when the PowerPC core executes cached instructions
  • Hardware vs software breakpoints

HARDWARE IMPLEMENTATION OF THE PPC440 CORE

  • External connections
  • Clock and power management interface
  • CPU control interface
  • Reset interface
  • External interrupt controller interface
  • Instruction-side local bus interface
  • Data-side local bus interface
  • DCR interface
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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