THE ARM ARCHITECTURE

• ARM operation modes
• The ARM registers set
• Program Status Registers
• Exception handling

ARM11 CPU ARCHITECTURE

• ARM11 superscalar pipeline operation
• Dynamic vs static branch prediction
• Out of order execution
• Return stack

MEMORY SUBSYSTEMS

• Cache basics
• Hit under miss
• Highlighting data flows between main memory, L1 cache and L2 cache
• Write buffer
• Tightly coupled memories
• Configuration & control through CP15

MEMORY MANAGEMENT & PROTECTION

• Introduction to page management
• V6 virtual memory architecture
• ARM V6 endianness
• Data alignment

ARMv6 INSTRUCTION SET

• Additional classes of instruction
• Standard multiply extension
• Long multiplication
• Packed data types

PRIMECELL VECTORED INTERRUPT CONTROLLER

• Primecell VICs
• Reducing interrupt latency through automatic vector generation
• Connectivity : daisy-chained VIC

TRUSTZONE

• TrustZone conceptual view
• Secure to non secure permitted transitions
• L1 and L2 secure state indicators, memory partitioning

INTELLIGENT ENERGY MANAGER

• Conventional power management
• IEM infrastructure and components
• Energy management principles
• Switching voltage levels

ARM1136 OVERVIEW

• New features compared to ARM9
• The four external bus interfaces : instruction fetch, data read, data write and peripheral port
• DMA between L1 TCMs and L2 memory system
• Low interrupt latency mode through VIC dedicated vector port
• Implementation flow overview, simulations models
• Reset and clocking
• Booting an ARM1136

ARM1156 OVERVIEW

• New features compared to ARM1136
• AXI (AMBA3) interfaces
• Thumb2 new instruction set
• Limitations of the MPU with regard to MMU
• Reset and clocking
• Booting

ARM1176 OVERVIEW

• New features compared to ARM1136 : IEM and TrustZone
• AXI (AMBA3) interfaces
• ARM1176 example system
• Reset and clocking
• Booting

ARM11 MULTI-PROCESSOR SYNCHRONISATION

• Introduction to semaphore
• Using the SWP instruction
• Using ARMv6 synchronisation instructions : LDREX, STREX and CLREX

AHB PROTOCOL

• Transfers with AHB
• Use of HREADY, HRESP & HTRANS signals
• Implementation of indivisible transactions

AXI PROTOCOL

• Topology : direct connection, multi-master, multi-layer
• PL300 AXI interconnect
• Separate address/control and data phases
• AXI channels, channel handshake
• Support for unaligned data transfers
• Transaction ordering, out of order transaction completion
• Atomic transactions

APB

• APB interconnect
• Read and write cycles
• APB in AMBA3

ARM11 DEBUG

• Basic debug requirements
• Embedded core debug
• Cache, smart cache(TCM) and MMU debug

TRACING AN ARM11-BASED SYSTEM