OVERVIEW

• 5-bus architecture, organization of a board based on MV6446X
• Frequency domains, fast path between CPU and SRAM / SDRAM
• Data integrity checking
• Internal crossbar
• Headers retarget

CPU INTERFACE

• CPU address space decoding
• CPU-to-PCI address remapping
• Arbitration, multi-processor operation
• Cache coherency
• Transaction ordering
• Hardware implementation

INTEGRATED SRAM

• Functional description, SRAM access arbitration
• Through vs CopyBack coherency
• ECC protection

DDR INTERFACE

• Introduction to DDR SDRAM from Jedec specification
• Initialization sequence
• Page management
• Read and write transactions
• Transaction ordering
• Cache coherency
• ECC and read-modify-write transactions
• Hardware implementation, SSTL technology

DEVICE CONTROLLER

• Functional description, transaction queue, read and write data buffers
• Connecting 8/16/32 bit devices
• Timing parameters
• External acknowledgement
• Pack / unpack and burst support

PCI INTERFACE

• PCI bus arbitration
• Master operation in PCI and PCI-X mode
• Target operation in PCI and PCI-X mode
• PCI-to-PCI configuration transactions
• Address decoding
• Cache coherency
• Messaging unit

GENERAL PURPOSE INPUT/ OUTPUT PINS

• Pin direction and polarity definition
• Interrupt request inputs
• Multi Purpose Pin multiplexing

INTERRUPT CONTROLLERS AND TIMERS

• Watchdog timer
• Timers / counters
• Interrupt controller functional description

TWSI CONTROLLER AND RESET

• Master and slave operation, 7- or 10-bit addressing
• Master write sequence, master read sequence
• Slave write sequence, slave read sequence
• Reset pins and configuration
• Serial ROM initialisation
• Requirement for an external Central Resource CPLD

IDMA CHANNELS

• IDMA address decoding
• Demand mode
• Normal mode vs chained mode
• Channel activation

XOR ENGINES

• State machine : Active, Inactive and Paused states
• XOR, CRC and DMA operation modes, format of transfer descriptors
• Memory Initialization operation mode
• ECC error cleanup operation mode
• Address decode windows
• Address override capability
• Cache coherency

MULTI-PROTOCOL SERIAL CONTROLLERS

• Address decoding
• Pinout, connection to MPP logic
• Baud Rate Generator
• MPSC clocking
• SDMA operation
• Transmit descriptor format, ring organization
• Receive descriptor format, ring organization
• HDLC mode, UART mode, Transparent mode

GIGABIT ETHERNET CONTROLLERS