ARM Cortex-M3 CORPORATE INTRODUCTION

• ARM architectural summary
• Architecture challenge, meeting the challenge with profiles
• ARM instruction set evolution

ARM Cortex-M3 INTRODUCTION

• Programmer's model
• Fixed memory map
• Privilege, modes and stacks
• Memory Protection Unit
• Interrupt handling
• Nested Vectored Interrupt Controller [NVIC]
• Power management
• Debug

DEVELOPMENT TOOLS OVERVIEW

• RVCT compilation tools
• Codewarrior for RVDS
• RVD debugger
• RVISS simulator
• JTAG run control unit
• Trace capture unit

ARM Cortex-M3 CORE

• Datapath and pipeline
• Write buffer
• Bit-banding
• System timer
• State, privilege and stacks
• System control block

THUMB-2 INSTRUCTION SET

• Data processing instructions
• Branch and control flow instructions
• Memory access instructions
• Exception generating instructions
• If...then conditional blocks
• Exclusive load and store instructions
• Accessing special registers
• Memory barriers and synchronization
• Workbook : introductory tutorial for Cortex-M3

INTERRUPTS

• Interrupt entry / exit, timing diagrams
• Tail chaining
• Interrupt response, pre-emption
• Interrupt prioritization
• Interrupt implementation configurability, impact on core size

EXCEPTIONS

• Exception behavior, exception return
• Non-maskable exceptions
• Privilege, modes and stacks
• Fault escalation
• Vector table

MEMORY TYPES

• Memory types, restriction regarding load / store multiple
• Device and normal memory ordering
• Access order
• Memory barriers

MEMORY PROTECTION UNIT

• Memory protection overview, ARM v7 PMSA
• Cortex-M3 MPU and bus faults
• Region overview, memory type and access control, sub-regions
• Setting up the MPU

EMBEDDED SOFTWARE DEVELOPMENT WITH Cortex-M3

• Placing code, data, stack and heap in the memory map, scatterloading
• Tailoring the C library to your target
• Reset and initialisation
• Building and debugging your image
• Long branch veneers
• Workbook : Retargeting the standard C library functions, handling interrupts

INVASIVE DEBUG

• Cortex-M3 debug features
• Monitor mode
• Flash patch and breakpoint features
• Data watchpoint and trace
• DWT registers
• AHB-Access Port

NON-INVASIVE DEBUG

• Basic ETM operation
• ITM stimulus port registers
• DWT trace packets
• Time-stamping packets
• TPIU components
• Serial Wire connection

C/C++ COMPILER HINTS AND TIPS FOR Cortex-M3

• ARM compiler optimisations
• Mixing C/C++ and assembly
• Coding with ARM compiler
• Measuring stack usage
• Local and global data issues, alignment of structures

AMBA3.0 INTERCONNECT SPECIFICATION

• Purpose of this specification
• Example of SoC based on AMBA specification
• Differences between AMBA2.0 and AMBA3.0

AHB - ADVANCED HIGH PERFORMANCE BUS

• Centralized address decoding
• Address gating logic
• Arbitration, bus parking
• Single-data transactions
• Sequential transfers
• Retry response
• Split response
• AHB-lite specification

APB - ADVANCED PERIPHERAL BUS

• Read timing diagram
• Write timing diagram
• Operation of the AHB-to-APB bridge
• APB3.0 new features

AHB CORTEX-M3 PORTS