• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Freescale
• Practical exercices are built with Diab Data compiler, downloaded onto a MPC8572E target board through the Lauterbach probe
• Trace32 debugger is used to control code execution

• MVD offers a training on RapidIO (Reference 002602A),
• MVD offers a training on PCI Express (Reference 003279A)
• MVD offers a training on an Ethernet and switching (Reference 003367A).

• Experience of a 32 bit processor or DSP is mandatory
• Knowledge of the RapidIO and PCI-Express bus is recommended

• The course details the Ocean crossbar operation
• Cache coherency protocol is introduced in increasing depth and the benefit of data stashing is explained
• The e500 core is viewed in detail, especially the SPU that enables Floating point and vector processing
• The boot sequence and clocking are explained
• The course details the hardware implementation of the MPC8572
• A long introduction to DDR2/3 SDRAM operation is done before studying the DDR SDRAM controller
• An in-depth description of the RapidIO port and the PCI-Express port is done
• The course highlights both hardware and software implementation of gigabit / fast / Ethernet controllers
• The course clarifies the operation of hardware acceleration mechanisms : Gigabit Ethernet TCP/IP offload engine, Pattern matcher and Table Lookup Unit

• Since this course will be delivered only on site, companies interested in attending it should select which topics have to be covered
• From the timing indications provided in this document, the syllabus of a tailored training can be defined
• Do not hesitate to contact us (guillaume.peron@mvd-fpga.com) to adapt the course to your specific requirements

(The full description of this course can be provided on request)

INTRODUCTION TO MPC8572

• Internal data flows, OCEAN switch fabric, packet reordering
• Implementation examples
• Address map, ATMU, OCEAN configuration
• Local vs external address spaces, inbound and outbound address decoding

THE e500 CORES

THE INSTRUCTION PIPELINE

• Dual-issue superscalar control
• Dynamic branch prediction
• Execution timing,

DATA AND INSTRUCTION PATHS

• Load store unit
• The LMQ
• Store miss merging and store gathering
• Memory access ordering

THE MEMORY MANAGEMENT UNITS

• Thread vs process
• The first level MMU and the second level MMU
• Snooping of TLBs
• TLB software reload
• Process protection, variable number of PID registers and sharing
• 36-bit real addressing

CACHES

• The L1 caches
• Cache coherency
• Level 2 cache
• Stashing mechanism

PROGRAMMING

• Differences between the new Book E architecture and the classic PowerPC architecture
• Signal Processing APU (SPU)
• PowerPC EABI : sections

EXCEPTIONS

• Book E exception handling
• Critical versus non critical
• Handler table
• Core timers

DEBUGGING

• Performance monitoring
• JTAG emulation
• Watchpoint logic

INFRASTRUCTURE

RESET, CLOCKING AND INITIALIZATION

• Platform clock
• Power-on reset sequence
• Power-on reset configuration
• Boot page translation

DDR2/DDR3 SDRAM MEMORY CONTROLLER

• DDR2 and DDR3 Jedec specification
• On-Die termination
• Calibration mechanism
• Mode registers initialization, bank selection and precharge
• ECC error correction
• Address decode
• Timing parameters programming

LOCAL BUS CONTROLLER

• Multiplexed or non-multiplexed address and data buses
• Dynamic bus sizing
• GPCM, UPMs
• NAND flash controller

SERIAL RapidIO INTERFACE

• RapidIO port
• Message Unit
• Programming inbound and outbound ATMUs
• Hot-swap support
• Error handling

PCI EXPRESS INTERFACE

• Modes of operation, Root Complex / Endpoint
• Transaction ordering rules
• Programming inbound and outbound ATMUs
• Configuration, initialization

PROGRAMMABLE INTERRUPT CONTROLLER

• Mixed mode vs pass-through mode
• Interrupt sources
• Understanding interrupt masking
• Interprocessor interrupts
• Nesting implementation

INTEGRATED DMA CONTROLLER

• Priority between the 4 channels
• Scatter / gathering
• Selectable hardware enforced coherency
• Ability to start DMA from external 3-pin interface

PATTERN MATCHER

• Objective of this unit
• Updating the pattern database
• Detecting patterns across packet boundaries
• Deflate engine

TABLE LOOKUP UNIT

• Exact match vs Longest prefix match
• Utilization in IPv6
• How software interact with the TLU unit

PERFORMANCE MONITOR AND DEBUG FEATURES

• Event counting
• Threshold events
• Watchpoint facility
• Trace buffer

INPUTS/OUTPUTS

THE ETHERNET CONTROLLERS

• Address recognition, pattern matching
• MII interface
• Buffer descriptors management
• Physical interfaces : GMII, MII, TBI or RGMII
• Layer 2 acceleration accept or reject on address or pattern match
• Direct queuing of four flows
• Management of VLAN tags and priority
• Quality of service
• IEEE1588 compliant time-stamping
• FIFO mode
• 10/100 Fast Ethernet Controller
• Buffer management
• MII interface

SECURITY ENGINE

• Overview of the encryption mechanism
• Introduction to DES and 3DES algorithms
• Data packet descriptors
• Crypto channels
• XOR acceleration

LOW SPEED PERIPHERALS

• Description of the NS16552 compliant Uarts
• Flow control signal management
• FIFO mode
• I2C protocol fundamentals
• Transmit and receive sequence
• GPIO configuration