Training - NXP LPC21XX/LPC22XX microcontrollers implementation ( reference 004748A)
 
    Related courses :
  • MVD is offering a course on CAN, reference 002601A
   
           
    Prerequisites
  • Experience of a processor or DSP is recommended
   
           
    Practical labs :
  • Labs are executed under GNU/Lauterbach environment
   
           
  Course Objectives
  • The course details the hardware implementation of the LPC2294 microcontrollers
  • The boot sequence and the clocking are explained
  • The training helps to become familiar with the development environment chosen by the customer
  • Practical labs on integrated peripherals are based on I/O functions provided by NXP
  • The course focuses on the low level programming of the ARM7TDMI core
  • The course provides examples of internal peripheral software drivers
   
           
    Duration
  • 4-day course
   
           
    Topics

(The full description of this course can be provided on request)

INTRODUCTION TO LPC2210 AND LPC2294

  • ARM core based architecture
  • ARM7 local bus
  • AMBA AHB/APB internal buses
  • The main three blocks : platform, core and input / output peripherals
  • APB Bridges
  • Memory mapping, internal flash (2294) and SRAM

ARCHITECTURE OF THE ARM7TDMI CORE

  • Presentation of the core, architecture and programming model
  • Operating modes : user, system, super, IRQ, FIQ, undef and abort
  • Pipeline, calculation of the CPI
  • Effects of branches and exceptions on the performance
  • ALU data path

SOFTWARE IMPLEMENTATION, V4T SPECIFICATION

  • Parameterizing the linker to define sections
  • Branch instructions, implementation of C call and return statements, long branch veneers
  • ARM vs Thumb instruction sets, interworking
  • ARM instruction set
  • Inline barrel shifter
  • Access to memory-mapped locations, addressing modes
  • Arithmetical and logic instructions
  • Thumb instruction set, highlighting restrictions with regard to ARM instruction set
  • Compiler hints and tips, optimisations supported by RVCT
  • Stack management
  • Benefits of condition set capability in ARM state
  • C-to-Assembly interface, ATPCS specification

EXCEPTION MECHANISM

  • Reset
  • FIQ vs IRQ
  • Exception return instructions
  • Latency estimation, impact of load and store multiple instructions
  • Organization of the handler table, priority decoder, pre-emption and nesting
  • ISR header and footer routines
  • Development of a generic exception handler

INTEGRATED DEBUG FACILITIES

  • JTAG interface
  • Debug facilities, hardware breakpoint
  • Executing code from RAM to take benefit of software breakpoints

THE VECTORED INTERRUPT CONTROLLER

  • Assigning a priority to each interrupt source
  • Steering external interrupts and local interrupts to either the core FIQ or IRQ
  • Developing a generic interrupt handler performing nesting according to peripheral priorities defined by the user
  • Integrated timers
  • Using timers to understand the operation of the VIC

SYSTEM CONTROL

  • Pin connect block
  • Clocking
  • Reset and wake-up timer
  • Low power modes
  • Watchdog timer
  • Real-Time clock

ON-CHIP FLASH MEMORY (2294)

  • Organization
  • Erase sequence
  • Program sequence
  • In system programming via serial port
  • On-chip bootloader

EXTERNAL MEMORY CONTROLLER

  • Address decoding
  • Chip-select registers
  • Parameterizing the memory bank registers to support external burst flash

SERIAL INTERFACES

  • I2C basics
  • I2C controller
  • UART controller
  • SPI and SSP interfaces
  • CAN protocol basics
  • CAN controller (2294)
   
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards.
   
           
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If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation