UDP Transmit engine Core
 
    Description

The MVD UDP Transmit engine core is a drop-in module that includes the following functions :
  • Full hardware UDP encapsulation
  • Full hardware IP encapsulation
  • Auto-increment of the identification IP field
  • IP fragmentation not supported
  • Support all current FPGA families
    
             
    Features

Transmit side UDP / IP / MAC stack, a real time UDP offload engine.

  • Programmable UDP source and destination ports
  • Programmable IP source and destination addresses
  • Programmable MAC source and destination address
  • JUMBO frame supported in option for Giga bit version
  • Multiple UDP port supported in option
  • Processor interface in option
    
           
    Applications

MVD UDP transmit engine may be used in applications related to Ethernet transmission such as VOIP or acquisition data.		    
           
           
                       
        The core is provided with a specific connection example with a configurable bus width interface to rapidly connect to your design.

Notice : For Xilinx target Virtex4 and Virtex 5, the MVD MAC or MVD GIGA MAC can be replaced by the TEMAC.		    
                       
      Documentation

    Contacts

Sales contact : info_cores@mvd-fpga.com
Technical support : support_cores@mvd-fpga.com