AES
     
         
  AES 128/192/256-bit encryption/decryption AES  
         
Description

The core is a drop-in module that includes the following functions :
  • 128/192/256-bit key size
  • Automatic Roundkey calculation
  • Encryption or decryption functions are implemented in the core
  Features
  • Implements AES (Rijndael) to latest NIST FIPS PUB 197
  • Drop-in module for Spartan®-6, Virtex®-6, Artix™-7, Kintex™-7 and Virtex®-7 FPGAs
  • Single clock
  • Supports 128/192/256-bit key size
  • Same core can be used for encryption and decryption
  • Automatic Roundkey generation inside the core
  • Update Key is allowed if an encryption or decryption process is running
  • ECB (Electronic Code Book) and CBC (Cipher Block Chaining) are supported (please contact MVD for other modes)
  • > 200Mbps @ 125MHz (AES-128)
  • > 170Mbps @ 125MHz (AES-192)
  • > 150Mbps @ 125MHz (AES-256)
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • Design delivered as Netlist
Applications

AES core may be used in applications related to MPEG-TS stream encryption, or any other encryption applications.

Companion core

AES MPEG TS Interface

   
Documentation
Product brief        
Data sheet        
           
Contact
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com