Application note- DVB transmission from MPEG-TS to RF output
MVD solutions for DOCSIS, EURODOCSIS, DVB-C (J83A/C), Cable Modulator (J83B), DVB-S, DVB-T and DVB-H

MVD offers a large range of complete solutions for DVB transmission. Engineering requirements and production costs are analyzed below in order to give you some guidelines for your particular application.

MVD DVB IP cores have been designed to take the best advantage of the latest generation low cost FPGAs. They provide the highest level of performance and flexibility. However, even if the core is an important part of the DVB transmitter design, we also have to consider the global solution to build a complete application able to convert your SPI (MPEG_TS) streams in a full compliant analog RF output according the required standards.

This app note analyzes the most common cases for DVB-C (J83A/C), Cable Modulator (J83B), DVB-S, DVB-T and DVB-H. It takes in consideration the engineering efforts, the time to market as well as production cost.

In addition, MVD provides extra support, design and production services to help you manufacturing your own, customized application at minimum risk and lowest development time.

Depending on your specific requirements, MVD recommends three different ways for implementing your own single channel or multi-channel transmitter.

All of those solutions are based on the use of a low cost FPGA as well as other electronic components :

  • FPGA requirements :

    A DVB transmission core is typically implemented by using relatively high speed logic as well as other FPGA advanced features like :
    • Internal memory blocks (single and dual port - for FIFO, sin/cos table and other)
    • High speed multipliers (for FIR filters, IF modulation, IFFT for OFDM - DVB-T/H)
    • Internal PLL or DCM for clock management

    For example, a DVB-C (J83A/C) IP core can be built by using the following resources :

    • 8000 Logic cells
    • 5 x 18-Kbit BRAM (or 10 x 9-Kbit BRAM)
    • Up to 12 x 18x18-bit multipliers
    • 1 PLL or DCM

    Typically, a DVB-C IP core can be implemented into a low cost Xilinx 3S500E FPGA, and also Altera CycloneIII EP3C10, or Lattice ECP2-12.

    As another example, a DVB-T IP core requires the following resources

    • 15000 logic cells
    • 48 x 18-Kbit BRAM (or 96 x 9-Kbit BRAM)
    • Up to 16 x 18x18-bit multipliers
    • 2 PLL or 2 DCM
  • Low cost DAC (AD9744) for IF output (30 to 58 Mhz)
  • Microtune MT5100 analog up converter module for up to 4-channel RF output (44 to 862 Mhz)
  • Analog Devices AD9789 RF DAC for up to 4 channel RF output (44 to 862 Mhz)
  • Maxim MAX5881 RF DAC + high performance Virtex5 FPGA for 16+channel RF output (44 Mhz to 2 GHz)
From MPEG-TS to RF using MVD FPGA IP cores + Microtune MT5100F Up converter
From MPEG-TS to RF using MVD FPGA IP cores + Analog Devices AD9789 2.4 MSPS TxDAC
From MPEG-TS to RF using MVD FPGA IP cores + Maxim MAX5881 4.3 GSPS DAC