Multi RTP TS Receiver
     
         
  Create DVB-SPI compliant stream from a UDP/(RTP) CBR Ethernet stream where MPEG-TS packets are not sent regularly (packets come in bursts) orsuffer from jitter. Multi RTP TS Receiver  
         
Description

All receiver equipments which have a DVB-SPI input must be fed with a stream
which respects the timing between each PCR packet.
The Multi RTP TS receiver is a module allowing to create DVB-SPI compliant
stream from a UDP/(RTP) CBR Ethernet stream where MPEG-TS packets are not sent regularly (packets come in bursts) or suffer from jitter.
In any case, the PCR values in the incoming encapsulated stream(s)
must be correct to ensure proper functioning.


  Features
  • Drop-in module for Spartan™-6, 7 Series and later Xilinx® FPGAs
  • Single clock 125 MHz (same clock as Ethernet clock data)
  • Supports up to 32 UDP(RTP) input streams
  • Automatic detection of the input stream type (UDP only or RTP)
  • Supports any packet length (from 1 to 7 TS, each 188 bytes length, encapsulated in UDP(RTP))
  • DVB-SPI compliant transport stream bus output Programmable Latency for PCR mode
  • Respects PCR Accuracy according to TR 101 290 standard (+/- 500ns) for CBR input stream
  • BYPASS mode available for VBR input streams
  • Auto-adjustment for a bitrate variation up to 32kbits without any discontinuity of the stream at the output
  • For a bitrate variation higher than 32kbits, the PCR calculation is restarted
  • CPU interface for configuration of the input streams
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • Design delivered as netlist (.ngc or .edif format)
Applications

The Multi RTP TS receiver can be used in applications related to IPTV reception.
   
Documentation
Product brief        
Data sheet        
           
Contact
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com