UDP CPU Interface
     
         
  MVD IP cores setting via Ethernet network UDP CPU Interface  
         
Features
  • Drop-in module for Spartan™-6, Virtex™-7, Artix™-7, Kintex™-7 an Zynq™ Xilinx FPGAs
  • Companion core for all MVD IP cores
  • Writing of main IP cores parameter settings
  • Status reading of main IP cores
  • Netlist version available for ISE and VIVADO
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Applications

The UDP CPU Interface IP core can be used with any MVD IP cores when local CPU is not available to configure them by using Ethernet network.

MVD UDP/IP Stack IP Core is mandatory to use this companion core.		    
Documentation
Product brief        
Data sheet        
   
Contact
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com