Description
MVD Cores develops IP cores which need DDR External Memory.
To spare resources or to allow more components to have access to DDR
memory, MVD has designed MCB interfaces ports Multiplexer N to 1 for
Xilinx® components.
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Features
- Drop-in module for, 7 Series and later Xilinx FPGAs
- 8 MCB input interface ports (each channel can be trimmed during implementation process)
- Can support unidirectional and bidirectional
- 1 MCB output interface which time multiplexed the inputs
- 32 bits data MCB interface port only
- Fully synthesizable RTL VHDL design (not delivered) for easy customization
- Design delivered as Netlist
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MCB Port Multiplexer N to 1
