SAP/SDP Inserter - IP core for FPGA
SAP/SDP Inserter
  SAP/SDP Inserter allows to send SAP/SDP packets for multicast stream announcements SAP/SDP Inserter  

Session Announcement Protocol (SAP) is a protocol to broadcast multicast session information. SAP was published by the IETF as RFC2974.

The core encapsulates Session Description protocol (SDP) as a description of streaming media information. SDP was published by the IETF as RFC4566.

SAP/SDP inserter sends periodically SAP/SDP announcements at Multicast address and UDP port 9875. These announcements allow the receivers which support SAP/SDP protocol to retrieve all the necessary information to connect to all streaming multicast media present.   

  • Drop-in module for Spartan™-6 and 7 Series Xilinx FPGAs
  • Single clock
  • Generates SAP Header and encapsulates SDP data into SAP packets
  • SDP description (ASCII) is sent through CPU interface
  • Can support up to 128 SAP/SDP Channels
    (if more channels are required please contact MVD)
  • Full synthesizable RTL VHDL design
    (not delivered) for easy customization
  • Design delivered as Netlist for ISE or  VIVADO
    (.ngc for Spartan-6 and .edn for 7 Series)

The SAP/SDP Inserter Core is an add-on module for the MVD UDP/IP Stack that allows to send SAP/SDP packets for multicast stream announcements on a local network.
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