Description
All receiver equipments which
have a DVB-SPI input must be fed with a stream which respects the
timing between each PCR packet.
The TS Jitter Cleaner IP core allows the transmission of an MPEG-TS
data stream made of 188 bytes packets to such a receiver equipment with
a DVB-SPI input.
The core is able to de-burst and de-jitter MPEG-TS packets of a CBR
stream. The output respects PCR accuracy timing according to TR 101 290
standard.
The core can be configured to use BRAMs memory (if input streams have
low jitter and/or bursts) or DDR memory (larger memory which permits to
manage input streams with higher jitter and/or burst). |
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Features
- Drop-in module for Spartan™-6 and 7 Series
Xilinx® FPGAs
- Single clock (125MHz or
higher)
- Supports CBR input streams only
- Supports any packet length input from 188 to
255 bytes
- Supports data packet or data burst format
- Supports either internal BRAMs or External DDR
memory
- Can manage up to 8 streams per instance
- Respects the PCR Accuracy according to TR 101
290 standard
(+/- 500ns)
- Auto-adaptation of frequency offset according
to TR 101 290 standard
(27MHz +/- 810Hz)
- Auto-adjustment for a bitrate variation up to
32kbits without any discontinuity of the stream at the output
- For a bitrate variation higher than 32kbits,
the core is restarted
- CPU interface for reading bitrate calculation
of the managed streams
- Full synthesizable RTL VHDL design (not
delivered)for easy customization
- Design delivered as Netlist (.ngc or .edif
formats)
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TS Jitter Cleaner
