440GP INTRODUCTION

• Block diagram
• Internal concurrent transfers examples
• Hardware introduction
• 440GP mapping
• Programming model
• Comparison between 440GP and 405GP

CORE-CONNECT

• PLB arbiter, OPB arbiter and PLB-to-OPB bridge configuration
• Bus errors recovering from syndrome registers
• PLB performance monitor

THE PowerPC CORE

• Pipeline operation
• Internal caches
• CCR0 register
• Speculative loads, storage ordering and synchronization : msync & mbar instructions
• MMU

BOOK E COMPLIANT CORE

• Branch instructions
• Addressing modes, load & store instructions
• Integer instructions
• 16-bit mac instructions
• Exception management
• Core timers
• PowerPC EABI
• JTAG emulator use
• Real time trace

CLOCKS, RESET AND POWER MANAGEMENT

• Clocks synthesizer
• Low power modes
• Reset
• Boot routine example
• IIC bootstrap controller

INTERRUPT CONTROLLER & GENERAL PURPOSE TIMERS

• Interrupt masking and acknowledgement
• Critical interrupt handlers using vectorization

THE INTERNAL SRAM

• Base address definition
• Access errors

THE DDR-SDRAM CONTROLLER

• DDR-SDRAM operation
• Jedec specification basics
• Hardware interface
• Bank activation, read, write and precharge timing diagrams
• ECC error correction
• Initial configuration following Power-on-Reset
• Address decode
• Timing parameters programming

THE EXTERNAL BUS CONTROLLER

• External bus pinout, driver enables
• Dynamic bus sizing
• Address decoding
• Timing parameters initialization
• Device-paced transfers
• External bus master interface

THE PCI-X BRIDGE

• Data flows
• Inbound an outbound transactions handling
• Address mappings
• Synchronization between CPUs : the MSI registers
• Boot modes, initialization / Reset sequence

THE 4 DMA CHANNELS

• The buffered transfer mode
• Related signals
• Channels bus priority
• Data packing / unpacking
• Buffers chaining

THE FAST ETHERNET CONTROLLER

• Frame format with and without VLAN option
• 440GP Ethernet controller organization
• PHY interface
• Hash table restrictions
• Buffer descriptors management
• Transmit sequence
• Receive sequence

THE UARTS

• The UART frame : break, idle, start, stop
• Transmission and reception FIFOs use
• Flow control signals management

THE IIC PORTS

• IIC protocol basics
• Transfer timing diagrams
• Transmit and receive sequences

MIGRATION FROM THE 440GP TO THE 440GX