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| Training - ColdFire 5x07 (reference
002592A) |
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Partners
- Do not hesitate to request the detailed
course description by contacting training@mvd-fpga.com
- This training course is approved by Freescale
- Practical exercices are built with Diab
Data compiler, downloaded on a
5307 target board through the EST
probe
- VisionClick debugger is
used to control code execution
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Related Trainings
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Prerequisites
- Experience of a 32 bit processor or DSP
is mandatory
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Course Objectives
- The course describes the ColdFire
assembly language and highlights
differences from 68K instructions
- An example of SDRAM controller
initialization is provided
- Interfacing with external devices is
explained
- The interrupt controller is viewed in
detail
- Interrupt driven DMA transfers are
studied
- A programming example has been developped
for each internal peripheral (serial;
I2C, timer)
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Duration
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Topics (The full description of this course
can be provided on request)
5307 INTRODUCTION
- Coldfire roadmap
- Differences between ColdFires and 68K
processors
- 5307 block diagram
- Memory mapped I/O organization
V3 CORE
- 5307 pipeline
- Programming model
- Addressing modes
- Instruction set
- Stack management, subroutine call and
return
- C to assembly interface
- Exception management
- Internal SRAM
- 5307 cache operation
HARDWARE IMPLEMENTATION
- Dynamic bus sizing
- Address decoding
- Arbitration
- Burst cycles
- Bus error management
DEBUG FACILITIES
- Intrusive vs non-intrusive debug
- BDM port
- Hardware breakpoints
- Trace port
THE SIM MODULE
- The interrupt controller
- The software watchdog
- Reset, self-configuration
- Clock synthesis
- General Purpose I/O pins
THE MEMORY CONTROLLER AND THE DRAM/SDRAM
CONTROLLER
- SRAM connection, chip-select programming
- DRAM / SDRAM basics
- The 5x07 (S)DRAM controller : address
decoding, refresh rate definition,
address multiplexing selection
THE SERIAL PORTS
- Asynchronous ports
- Transmit and receive sequences
- Synchronous port : I2C basics
- Transmit and receive sequences
THE DMA CONTROLLER
- Single address vs dual address transfers
- Hardware interface, hardware initiated
transfers
- Programming model
THE TIMERS
- Capture mode
- Period selection
- Interrupt control
5407 ENHANCEMENTS
- V4 core enhancements
- Instruction set additions
- Enhanced memories
- On-chip DMA and serial ports
modifications
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Documentation
Training manuals will be given to participants
during training. Precise and easy of use, those
notes can be used as a reference afterwards. |
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