HCS12 MICROCONTROLLER FAMILY INTRODUCTION

• HCS12 microcontrollers architecture
• Differences between HC12 and HCS12 families

THE STAR12 CORE

• The instruction pipeline
• Branch instructions
• Addressing modes
• Arithmetic and logic instructions
• Bit instructions, shift and rotate instructions
• Mac instructions
• Interpolate instructions
• Stack management
• C-to-assembly interface
• Low power modes

EXCEPTION MANAGEMENT

• Exception management sequence
• Vectorization
• Exception priority
• Reset

DEBUG FACILITIES

• Hardware vs software breakpoints
• BDM protocol
• Securing the microcontroller

SYSTEM ON CHIP APPROACH

• Core interface signals
• External bus signals
• Clock and reset generator module
• PLL operation
• Core wake up

THE SIM MODULE

• Chip select programming
• Internal RAM and EEPROM base address selection
• Input / output parallel port configuration

MC9S12DP256B HARDWARE IMPLEMENTATION

• Signal descriptions
• Bus operation
• Timing diagrams

THE FEPROM

• Erase sequence
• Program sequence
• Test mode

THE EEPROM

• Erase and program clock selection
• Byte, page or block erase
• Program sequence

THE INTERRUPT CONTROLLER AND THE SYSTEM TIMERS

• Vector table description
• The COP
• The real time interrupt

THE ENHANCED CAPTURE TIMER MODULE

• Capture inputs
• Compare outputs
• Pulse accumulators

THE PWM GENERATORS

• Period and duty cycle selection
• Left or center aligned output modes

THE COMMUNICATION CONTROLLERS

• SPI controller : master vs slave selection
• Polarity selection
• UART controller
• Bit rate selection
• Point to multipoint communication : receiver wake up modes
• I2C Timing diagrams
• Transmit and receive sequences
• The MSCAN controllers
• Message buffers structure
• Timing and synchronization
• Error management
• Low power modes

THE ADC