INTRODUCTION TO DIGITAL SIGNAL PROCESSING

• Arithmetic processing of real-time signals
• Modified dual Harvard architecture : the X-memory and the Y-memory
• MAC operation
• DSP 563XX family introduction

563XX ARCHITECTURE

• Core busses
• Processing states
• Reset
• 56L307 mapping

THE DSP CORE

• The Data ALU
• The Address Generation Unit
• The Program Control Unit
• The instruction set
• C-to-assembly interface
• The PLL
• The 563XX instruction cache
• Exception management
• The debugging support
• MethJTAG use to access the OnCE

HARDWARE IMPLEMENTATION

• External memory addressing
• Arbitration protocol
• SRAM interface
• DRAM basics
• DRAM interface

THE DMA CONTROLLER

• Overlap between DMA channel and core
• Channel priority
• Triggering modes
• Circular buffer management

THE HOST INTERFACE

• Host interface description
• Transfer modes
• Handshaking protocols
• DMA access to HTX and HRX data registers
• Boot up using the HIO8 host port
• Programming model : host-side and DSP-side register banks

THE TRIPLE TIMER MODULE

• Timer related pins
• Triple timer modes
• Event capture
• Signal width / period measuring
• PWM
• Watchdog modes

THE ENHANCED SYNCHRONOUS SERIAL INTERFACE

• ESSI signals
• Network mode
• On-Demand mode
• ESSI exceptions
• Transmit and receive sequences

THE SERIAL COMMUNICATION INTERFACE

• SCI block diagram
• Asynchronous vs synchronous operation modes
• Baud rate selection
• Bootstrap loading from the SCI
• Asynchronous transmit and receive sequences

THE ENHANCED FILTER COPROCESSOR