Training - CompactPCI bus (reference 002598A)
 
        This training covers PCI bus implementation [4-day] and Compact PCI additional requirements [1-day].
If the PCI bus is already known, it is possible to register only for the last day of the course.		    
           
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • PCI timing diagrams are captured thanks to the VSYSTEMS Analyser board
  • Jungo WinDriver PCI driver kit is used to explain how to quickly develop a device driver for Windows
    • Practical labs help to become familiar with this tool
  • Notice that MVD is a reseller of Jungo softwares
    
           
    Related Trainings
  • The PCI-X training whose reference is 002597A is an extension to the PCI training, this is a 2-day on-site only course
  • MVD also offers a PCI Express training, reference 003279A
  • MVD delivers several courses on processors that include a PCI interface : AMCC 405GP, 440EP, 440GX, Freescale MCF548X, MPC834X, MPC85XX
  • A specific course details the implementation of the Xilinx PCI logicore (reference 002841A)
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
   
           
    Prerequisites
  • Experience of a digital bus is mandatory
  • Experience of a 32-bit processor is recommended
    
             
  Course Objectives
  • The training has been designed from the PCI3.0 specification
  • In details view of read prefetch / write posting mechanisms and synchronization rules
  • Transfer protocol understanding with the assistance of the VSYSTEM analyser board
  • The course emphasizes the host bridge operation especially the management of PCI accesses targetting cache enabled regions
  • A software routine has been developped to show how to access the configuration space
  • PCI initialization program description : interrupt requests allocation, memory regions allocation
  • PCI performance tuning : selecting optimized LT value, appropriate master priority, enabling fast-back-to-back
  • Focus on Compact PCI hardware interface
  • Hardware and software additional requirements to support hot swap
  • Implementation of a non-transparent 21554 intel PCI-to-PCI bridge frequently used in Compact PCI systems
    
           
    Duration
  • 5-day course
    
           
    Topics

(The full description of this course can be provided on request)

OVERVIEW

  • PCI specifications history
  • PCI bus features
  • PCI device types
  • Technological introduction
  • Architecture of recent PCs

PCI DEVICE ARCHITECTURE

  • Information buffering
  • Buffer management
  • Prefetchable vs non-prefetchable memory ranges
  • Synchronization rules
  • Producer / consumer model
  • Optional processings
  • PCI bus limitations

TRANSFER PROTOCOL

  • Transfer basics
  • Pinout, signal classes
  • Arbitration
  • Data transfer protocol
  • Address decoding in IO, MEM and CFG spaces
  • 64-bit data transfer
  • 64-bit addressing
  • Master initiated terminations
  • Target initiated terminations
  • Fast back-to-back
  • Parity control
  • Shared resource management
  • Bus analyse, benefit of a bus analyser / exerciser

INTERRUPTS AND RESET

  • PCI interrupts
  • Interrupt acknowledge transaction
  • Interrupt sharing
  • Message Signaled Interrupts
  • MSI-X
  • Reset, operating states :

CACHE COHERENCY

  • Cache basics
  • Snooping basics
  • Cacheability of RAM accessed by the host CPU through PCI
  • PCI masters accessing the host memory
  • PCI agent processor accessing the host memory

ELECTRICAL SPECIFICATION

  • Switched wave switching vs Incident wave switching
  • Static specification
  • Dynamic specification : 33 MHz and 66 MHz
  • Clocking
  • Decoupling
  • Routing and layout recommendations
  • Compliance checklists

CONFIGURATION SPACE

  • Configuration space mappings
  • Register description
  • PCI MEM and PCI IO mappings building
  • Expansion ROM
  • Capability list
  • Configuration transactions, IDSEL routing
  • Local vs distant CFG transaction
  • Generation of config transactions

PCI-TO-PCI TRANSPARENT BRIDGES

  • Bus numbering
  • Address decode, transaction forwarding rules
  • Distant configuration cycles
  • Error management

POWER MANAGEMENT

  • Bus power state machine
  • PCI function power state machine
  • Programming interface

PCI BASED INDUSTRIAL SPECIFICATIONS

  • Passive bus PICMG PC
  • CMC/PMC mezzanine boards, BUSMODE pins management
  • CompactPCI introduction
  • PC104+ introduction
  • PC.MIP introduction

THE CompactPCI SPECIFICATION

  • Backplane design rules
  • Board design rules
  • Electrical requirements on the system board

HOT SWAP

  • Architecture model, compliance levels
  • Hot swap additional signals
  • Insertion & extraction sequences

THE NON-TRANSPARENT 21554 PCI-TO-PCI BRIDGE

  • Address decoding
  • I2O specification objectives, implementation in the 21554
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
    Other trainings :

If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation