• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• The intent of this course is to help “bridge the gap” between the DSP Algorithm/System Designer and the Hardware Engineer. As well as describing how the algorithms can be efficiently implemented, the techniques will also demonstrate which decisions, at the system level, have the greatest impact on the implementation process and product costs.

WHO SHOULD ATTEND ?

• Although the course includes some very basic revision of some DSP algorithms, it is expected that a student has a fundamental understanding of digital signal processing theory and an appreciation of the principles of the following:
  • Sample rates
  • FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filters
  • Oscillators and Mixers
  • FFT (Fast Fourier Transform) algorithm
• It has been most beneficial for companies to send small teams that among them have a mixture of skills. Attendees should bring their favorite engineering/scientific calculator with them, as this will prove to be very useful in working examples and exercises

• Describe how DSP algorithms can be efficiently implemented using Xilinx FPGA technology
• Establish methods for the accurate estimation of silicon area consumed and hence costs
• Evaluate which algorithms are best suited to FPGA implementation and understand which algorithms are less desirable
• Observe how system level decisions impact the hardware implementation, and that the hardware implementation can enhance the results at the system level
• Investigate the use of Xilinx CORE Generator to realize typical DSP algorithms

• 3-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

Day 1

• Course Introduction / Agenda
• Basic terminology and acronyms used in DSP design
• Sample rates and bit widths used in DSP applications
• DSP Building blocks and processing requirements
• Numbering formats, range and precision
• Mathematical operations using a variety of formats
• Structure and resources of Xilinx devices
• Estimating DSP building block sizes

Day 2

• Implementing the multiplication function
• Bit width impact on system level decisions
• CORE Generator functions and capabilities
• Block versus Distributed memory
• SRL16E and the delay function
• Memory aspect ratios and their manipulation
• FIR filter specifications and implementations
• Selection of a technique for a given specification
• Effects of halfband and interpolated filters
• Creating an SDA FIR filter with CORE Generator

Day 3

• Options to be considered with multiple channels
• Interpolation and Decimation
• Rate changing and how it affects FIR filter choice
• Filtering algorithms that exploit device architecture
• Importance of connectivity versus isolated functions
• Numeric Controlled Oscillators and Mixers
• Using the FPGA as an efficient Co-Processor
• Strategies for FFT implementation
• Achieving bandwidth requirements of the FFT

COURSE EXERCISES

• Sample Rates & Bit Widths
• MAC Rates & Memory Requirements
• Constructing a 128 Tap FIR filter
• Fractional Number Formats
• Two’s Complement Arithmetic
• Summation by Addition Tree
• Summation by Addition Chain
• Full Adder – How many slices?
• Summation Structure Sizes
• Serial Processing
• An 8 bit × 12 bit Multiplier
• KCM Multipliers
• Size Estimates for Delay Structures
• Creating Larger RAM structures
• Selecting a MAC FIR Technique
• Parallel FIR Filter Size
• SDA Filter Implementation
• Symmetry, Interpolation and Phases
• Decimation Filter
• “fs/4” Mixing and Decimation
• Running (Moving) Average Filter
• Designing a Numeric Controlled Oscillator (NCO)
• The FFT – Benchmarks and Transform Time
• Data Block Collection and FFT Processing Time
• 128-point FFT in 1.28S