• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This PCI training course gives you an introduction to basic PCI concepts and architecture. The course emphasizes and illustrates how PCI transactions take place. It also gives an overview of Xilinx PCI solutions and includes a lab that illustrates the general design flow from core to verification.

• For intensive design training on Xilinx PCI products and to learn the basics of Xilinx PCI COREs, take the Xilinx Designing a PCI System (Ref. 002841A) course
• For training on the PCI-X Addendum to the PCI Local Bus Specification and a detailed investigation into the operation of the PCI-X LogiCORE, register for the Xilinx Designing for PCI-X (Ref. 002842A) course

• Working experience with digital design
• Basic knowledge of Verilog or VHDL
• Some experience with Xilinx Alliance Series™ or Xilinx Foundation™ tools
• Some knowledge of PCI is recommended

• Reduce design time by using Real-PCI from Xilinx
• Use leading-edge technology
• Real...
  • Compliance
  • Performance
  • Flexibility
  • Availability

After completing this training, you will be able to :

• Explain the basics of the PCI specification
• Describe the basics of the PCI local bus architecture
• Identify PCI signals and their general functions
• Describe how PCI signals are used to perform basic PCI bus operations
• Describe PCI addressing and bus commands
• Describe configuration functions and characteristics
• Describe how transactions are carried out on a PCI bus
• Identify issues with 64-bit/66 MHz PCI
• List and describe PCI variations
• Select the appropriate PCI solution for a specific application
• Describe the basic Xilinx PCI design flow

• 1-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

• Introduction
• PCI Local Bus Architecture
• PCI Signals
• Basic Bus Operations
• PCI Addressing and Bus Commands
• PCI Configuration
• Lab 1: Simulation of PCI Bus Transactions
• 64-Bit and 66 MHz PCI
• Xilinx PCI Solution
• Lab 2: Synthesis and Implementation

LAB DESCRIPTIONS

• Lab 1: Simulation of PCI Bus Transactions: This lab demonstrates typical PCI bus transactions and the signals associated with each type of bus transaction. The relationship between various signals is identified.
• Lab 2: Synthesis and Implementation: This lab demonstrates the Xilinx PCI design flow, from web-based core customization and download through synthesis to an implementation targeted for a device that supports Xilinx PCI using ISE 4 software GUI. The lab uses the example "Ping" design (included with the Xilinx PCI core) to target a Virtex-II device. Similar steps can be followed for other device families. You will use ISE 4 software to conduct this lab. It will guide you on how to enter the design, synthesize the design, and implement it using some of the software options and switches