THE V2 COLDFIRE CORE

• ColdFire core versions
• V2 pipeline
• Description of assembly instructions
• Mac instructions, implementation of a fixed point DFT
• ColdFire instruction set architecture enhancements
• Stack management, subroutine call and return
• C to assembly interface, organization of the stack frame
• Section definition
• Exception management
• 5282 2-kb cache operation, direct-mapped organization
• Cache coherency and invalidation, software control
• Internal 64-kb SRAM
• 512-kb Flash module map, program, erase and verify sequences, CFM configuration field, security key
• Power management

DEBUG FACILITIES

• Intrusive vs non-intrusive debug
• BDM port
• Hardware breakpoints
• Trace port

RESET

• Reset control flow
• Chip mode selection
• Boot device selection
• Configuration of the General Purpose Input / Output pins

DEVICE CONFIGURATION

• System Control Module, software watchdog, selection of Internal Peripheral System Base Address
• Internal bus arbitration
• Clocking
• The interrupt controllers

HARDWARE IMPLEMENTATION

• Dynamic bus sizing
• Address decoding
• External master interface
• Bus error management
• The memory controller
• The SDRAM controller

TIMERS

• Programmable Interrupt Timer Modules
• General Purpose Timer Modules
• DMA timers

THE DMA CONTROLLER

• Dual address transfers, continuous-mode or cycle-steal transfers
• Auto-alignment
• Hardware initiated transfers
• Burst transfers
• Automatic transfer of characters received or transmitted by an UART through a DMA channel

COMMUNICATION CONTROLLERS

• The 3 UARTs
• Connection with DMA channels
• Transmit and receive sequences
• The QSPI
• SPI protocol basics
• Command queue
• Transmit and receive sequences
• The I2C controller
• I2C protocol basics
• Transmit and receive sequences
• The FlexCAN controller
• CAN protocol basics
• Message buffers
• Mask registers
• Receive and Transmit processes
• The Fast Ethernet Controller
• Ethernet basics
• MII hardware interface
• Buffer management, buffer chaining
• Address filtering, use of hash tables
• Full duplex operation, flow control
• Receive and transmit sequences

QADC MODULE