Training - Virtex PowerPC System Implementation (reference 002952A)
 
      Notice
  • This training has been designed to show the capabilities of the powerpc405 Virtex-II Pro technology using Embedded Development Kit
  • It is a good way to discover the development environment required to develop Virtex-II Pro applications
  • This is the only Virtex-II Pro open class that is held periodically
    
           
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • This training course is approved by IBM microelectronics, Xilinx and Wind River
  • Practical exercices are built with GNU compiler, downloaded onto the Virtex-II Pro evaluation board through the Xilinx Probe
  • GDB debugger is used to control code execution
    
           
    Related Trainings
    
           
    Prerequisites
  • Experience of a 32 bit processor or DSP is mandatory
  • Experience of FPGA design is recommended
    
             
  Course Objectives
  • An introduction to the PPC405 core is done
  • The design of project facilitates the understanding of the hardware design flow and software design flow
  • Software and hardware debug strategies are highlighted
  • Optimization using profiling library and customer IP is covered
  • The course explains how a Virtex-II Pro System-On-Chip may be simulated as well as Bus Functional Model simulation
    
           
    Duration
  • 4-day course
    
           
    Topics

(The full description of this course can be provided on request)

VARIOUS SYSTEM ON CHIP OFFERED BY XILINX

  • Picoblaze
  • Microblaze
  • PPC405

THE PPC405 CORE ARCHITECTURE

  • Pipeline
  • MMU
  • Cache
  • Load/Store Buffer

HARDWARE IMPLEMENTATION OF THE PPC405 CORE

  • Clock and power management
  • CPU control interface
  • Reset interface
  • External Interrupt Controller
  • Busses
  • JTAG interface
  • FPGA Specific signals

EDK OVERVIEW

  • Introduction
  • XPS

THE HARDWARE FLOW

  • MHS file
  • SoC Hardware Specification
  • IP Definition files
  • Platgen and Implementation tools

POWERPC EABI

  • Architecture objectives
  • Programming model
  • PowerPC EABI
  • Exception management
  • Timer

THE SOFTWARE FLOW

  • Code generation steps
  • MSS file
  • Software Platform Specification
  • Xilinx Peripherals Drivers
  • CSP
  • GNU Linker Script
  • Cstart
  • Xilinx Libraries
  • Libgen
  • Software Applications Creation
  • Update Bitstream

INTEGRATED DEBUG FACILITIES

  • Overview
  • Debug Logic Related Registers

DEBUGGING A VIRTEX-II PRO APPLICATION

  • XMD
  • GDB
  • Chipscope Pro

OPTIMIZATION

  • Profiling
  • Create a customer IP

SIMULATION

  • SOC Simulation
  • BFM Simulation
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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