Training - PCI Express bus (reference 003279A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • Timing diagrams are taken from a PCI Express evaluation board thanks to the Lecroy Analyser board
   
           
    Related Trainings
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
   
           
    Prerequisites
  • Experience of a high speed digital bus like PCI / PCI-X is recommended
    
             
  Course Objectives
  • Packet switching benefits compared to shared busses are highlighted
  • The course explains the various traffic types that PCI Express supports
  • The use of virtual channels to match Quality of Service requirements is explained
  • The course describes the discovery sequence required to initialize the switches
  • The course details the various stages of the physical layer : 8b10b coding, scrambling, elastic buffer, clock recovery and link training sequence
  • The new features of the revision 2.0 are described
    
           
    Duration
  • 3-day course
    
           
    Topics

(The full description of this course can be provided on request)

THE TRANSITION TO PACKET SWITCHING

  • PCI bus limitations
  • The hub link bus
  • PCI-X
  • Solutions to increase the performance : differential transmission, packet switching

INTRODUCTION TO PCI EXPRESS

  • Overview
  • Topology
  • Layer protocol
  • Quality of Service
  • The physical layer

THE PHYSICAL LAYER

  • 8-bit / 10-bit coding
  • Scrambling
  • The ordered sets
  • Elastic buffer operation
  • Link training, detailed step-by-step sequence
  • Jitter budgeting and measurement
  • The electrical interface
  • Calibration channel characteristics

POWER MANAGEMENT

  • Link state power management
  • PCI Power Management software interface
  • Native PCI Express power management mechanisms
  • Power budgeting capability

PACKET ROUTING

  • PCI basics
  • Operation of PCI-to-PCI transparent bridge
  • Packet routing by the address
  • Packet routing by the ID
  • Packet routed implicitely

TLP ACKNOWLEDGEMENT

  • Acknowledgement objectives
  • Counters / timers present in the transmitter and the receiver
  • Sequences
  • Cut-through switches

QUALITY OF SERVICE

  • Introduction
  • VC arbitration
  • Port arbitration, switch model

FLOW CONTROL

  • Overview, transmit credit principle
  • Related counters
  • Credit update frequency

TRANSACTION ORDERING

  • PCI Producer / Consumer model
  • Relaxed ordering permitted by PCI-X
  • PCI Express transaction ordering rules

PACKET FORMAT

  • Benefits of a packet oriented protocol
  • TLP format
  • DLLP format

INTERRUPT MANAGEMENT

  • Message Signaled Interrupts
  • PCI Express Interrupt Management

ERROR MANAGEMENT

  • General principles
  • PCI-like error management
  • PCI Express basic error management
  • PCI Express basic advanced error management

THE CONFIGURATION SPACE

  • Root Complex Register Block [RCRB]
  • PCI Express enumeration
  • PCI-compatible configuration registers
  • Expansion ROMs
  • New features of PCI Express 2.0 :
  • PCI Express Enhanced Configuration Access Mechanism
  • Device serial number capability
  • Root Complex link declaration capability
  • Root Complex internal link control capability
  • ACS extended capability

DEBUGGING A PCI EXPRESS SYSTEM

  • Compliance lists
  • The Serial Data Analyser from Lecroy, test of the physical layer
  • Protocol analyser / exercicer from Lecroy
  • Trace analysis
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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