Training - VHDL - Language Introduction (reference 003342A)
 
      Presentation

This training course is aimed for electronic engineers with a good knowledge in digital systems design, wanting to acquire the VHDL language basics, in order to betterunderstand its capabilities in the context of logic synthesis and simulation.
Numerous practical exercises illustrated with demonstrations provide a good understanding of the basic principles through the writing of generic and synthesizable code and its associated simulation testbench, allowing to verify a proper operation.

    
           
    Duration
  • 3-day course
    
           
    Program

The entity - architecture pair

  • Main rules to observe for port declarations
  • Internal signals declaration
  • Examples

Synthesis Logic frequently used objects

  • Signals, variables, constants

The predefined types

  • Bit, bit_vector - limitations for these types
  • Booleans
  • Integers
  • " user defined " object types

STD_LOGIC et STD_LOGIC_VECTOR types and STD_LOGIC_1164 package

  • Advantages over predefined types for use in logic synthesis and simulation
  • Simulators and synthesizers interpretation.

Predefined operators and extended use to STD_LOGIC_VECTOR

  • Logic operators
  • Relational operators - known traps
  • Arithmetic operators

Rules to observe for Data vectors assignment

  • Typical examples

Concurrent Instructions and rules of use

  • When ... else
  • With ... select
  • For ... generate
  • Implementing a design example including
    • Multiplexers
    • Comparators
    • 7-segment decoder

Sequential instructions and their rules of use

  • If ... else
  • Case
  • For ... loop
  • Design example, synchronous counters
    • Initializable
    • Loadable
    • Up-Down
    • Cascadable
  • Implementation and simulation of a state machine
  • Example design implementations to illustrate the fundamental characteristics of these instructions

Introduction to simulation with VHDL Language

  • Several new instructions exclusively related to simulation
  • After
  • Wait for
  • Simulating the example designs developed previously

Hierarchy management and structured VHDL

  • How to split a design in interconnected modules
  • Use of cores and IP
  • Use of primitives, specific to the targeted technology, and their simulations

Predefined attributes and generic notions

  • Range, reverse_range, length, left, right...
  • Example of use
  • Introduction of sub-programs ( functions and procedures), and illustration of generic use
  • Implementation of a hierarchical design of a microprocessor interface and programmable timer with an interruption line
    
           
    Notes importantes

This training course has been developed by highly experienced digital electronics circuits design engineers. Its tutorial approach allows to comprehend the interest of having a real design methodology, and facilitates its implementation by an anticipation approach. Its duration can be adapted according to specific needs and prior experience of the audience.
The methodology presented here is applicable to the development of any type of digital circuit, regardless of the target (ASIC, FPGA, CPLD, electronic board) and development toolset, thanks to the generic aspects of the VHDL language.
For a smoother training flow, examples developed for logic synthesis are reused later for the simulation's practical exercises.
MVD recommends and provides for pratical exercises, the following tools :
  • Logic Synthesis : XST (Xilinx) or Synplify-Pro (Synplicity)
  • Simulation : ModelSim
  • Physical implementation : Xilinx ISE 6.x

However other synthesis, simulation, and physical implementation tools can be used on demand. Please consult us for any particular need.

   
           
    Computer hardware configuration for optimal operation
  • Pentium IV-based PCs or equivalent
  • Windows 2000 or XP
  • 2 Gbyte free space on HDD
  • 512 MByte RAM
  • CD-ROM Drive
  • Screen resolution: 1024 x 768 or greater

For on-site sessions, an LCD projector is to be provided

   
           
    Documentation

Training material in french language is provided to participants. Accurate and easy to use, they can serve as reference in future use. The exercises listings are also provided to the participants. 		   
           
    Other trainings :

If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation