Training - VHDL - Advanced Design Methodology (reference 003343A)
 
      Presentation

This training course is aimed for electronic engineers with a good knowledge in digital systems design, wanting to acquire a solid design methodology, and take the best profit from the VHDL language and the associated synthesis and simulation tools.

Numerous practical exercises with demonstrations allow to verify the pertinence of this methodology by using an appropriate VHDL coding style that permits an efficient, easy-to-debug and re-usable implementation.

    
           
    Duration
  • 3-day
    
           
    Program

Important review on VHDL coding recommendations for logic synthesis

  • Predefined operators, extended use with standardized packages
  • Process
    • Importance of the sensitivity list
    • Variables use
  • Typical traps to avoid
  • Potential interpretation inconsistencies between logic synthesis and simulation : how to overcome them ?
  • Practical exercises

Hardware design methodology in logic synthesis

  • Asynchronous design and typical pitfalls
  • Metastability and operating failure risk
  • Functional simulation limitations and timing issues on asynchronous designs : how to overcome ?
  • Synchronous design - advantages - methodology - debug techniques
  • Static timing analysis: how to use it ?
  • Performance optimisation regardless of the target
  • Pipeline introduction
  • Asynchronous events management
    • Aléatoires
    • Flots de données
  • Practical exercises

In-depth VDHL study for code optimisation and reuse in logic synthesis

  • Introduction to variables and examples of use
  • Genericity and automatic reusable modules re-parametering
  • Useful predefined attributes in logic synthesis
  • Functions and procedures
  • Packages and librairies definitions
  • Practical exercises

Hierarchy management for a better reusability

  • Organising a design by functional modules : which partitioning to use ?
  • Introduction to inference and instantiation
    • When to instantiate primitives or macros ?
    • Recommendations for writing evolutive/reusable code
  • Importance of choosing modules and nets nans to ease the physical implementation, simulation and debug
  • Should hierarchy be preserved during the logic synthesis ?
  • Practical exercises

Test benches and simulation

  • Some basic rules for writing an efficient test bench
  • Simulation-specific VHDL instructions
    • "Wait" and its various forms
    • "Loop" iterations
    • Assertions
    • Data types
    • others
  • Writing of components models in order to make the simulation more realistic
  • Use of existing simulation packages and models
  • Practical exercises
  • "pseudo-logic" integration for an easier interpretation of simulation results
  • Writing / reading ASCII files
    • Dataflow assignment from a file
    • Data results file storage
  • Command interpreter
  • Generating Information messages
  • Practical exercises
    
           
    Important Notes

This training course has been developed by highly experienced digital electronics circuits design engineers. Its tutorial approach allows to comprehend the interest of having a real design methodology, and facilitates its implementation by an anticipation approach. Its duration can be adapted according to specific needs and to the prior audience 's experience.

The methodology presented here is applicable to the development of any type of digital circuit, regardless of the target (ASIC, FPGA, CPLD, electronic board) and development toolset, thanks to the generic aspects of the VHDL language.

For a smoother training flow, examples developed for logic synthesis are reused later on for the simulation's practical exercises.

The "optimisation" code aspects for different types of target, are function of the chosen synthesis tools ( and their performance results on any particular target ). They can be considered in order to better understand the tools choice 's impact on results obtained on the selected target.

MVD recommends and provides for pratical exercises, the following tools :
  • Logic Synthesis : XST (Xilinx) or Synplify-Pro (Synplicity)
  • Simulation : ModelSim
  • Physical implementation : Xilinx ISE 6.x

However other synthesis, simulation, and physical implementation tools can be used on demand. Please consult us for any particular need.

    
           
    Computer hardware configuration for optimal operation
  • - Pentium IV-based PCs or equivalent
  • Windows 2000 or XP
  • 2 Gbyte free space on HDD
  • 512 MByte RAM
  • CD-ROM Drive
  • Screen resolution : 1024 x 768 or greater

For on-site sessions, an LCD projector is to be provided

   
           
    Documentation

Training material in french language is provided to participants. Accurate and easy to use, they can serve as reference in future use. The exercises listings are also provided to the participants. 		   
           
    Other trainings :

If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation