• ColdFire core versions
• Architecture of a typical 548X board
• Mapping of internal resources

THE V4e COLDFIRE CORE

• Pipeline basics
• Description of assembly instructions
• Floating Point Unit description
• Mac instructions, implementation of a fixed point DFT
• ColdFire instruction set architecture enhancements
• Stack management, subroutine call and return
• C to assembly interface, organization of the stack frame
• Position dependent code vs position independent code
• Section definition
• Exception management : vector table, priority, masking, precise faults
• Memory Management Unit : translation and access control, process protection
• TLB initialization
• Cache basics
• 32-kB cache data and instruction, a four-way set associative organization
• Cache coherency and invalidation, software control
• Internal 32-kB SRAM, initialization code
• Power management

DEBUG FACILITIES

• Intrusive vs non-intrusive debug
• BDM port
• Hardware breakpoints
• Trace port

RESET

• Reset sources
• Clocking, system clock generation, PLL control, loss of clock detection
• Reset control flow
• Requirements of the boot routine

SIU & INTERRUPT CONTROLLER

• System Control Module
• Internal bus arbitration
• The interrupt controllers : vectorized vs auto-vectorized mode, edge Port Module

HARDWARE IMPLEMENTATION

• Electrical specification, supply voltage sequencing
• Flexbus
• DDR SDRAM basics
• DDR SDRAM Controller
• PCI Controller
• Error management

TIMERS

• Programmable Interrupt Timer Modules
• General Purpose Timer Modules
• Input capture capability

THE MULTI CHANNEL DMA CONTROLLER

• DMA task memory
• DMA sources
• Transfer control descriptors

COMMUNICATION CONTROLLERS

• The PSC Module
• The DSPI
• The I2C controller
• The FlexCAN controller
• The Fast Ethernet Controller
• The USB 2.0 device controller

INTEGRATED SECURITY ENGINE