INTRODUCTION TO 440EPx

• Internal bus organization : dual PLB, OPB, DCR
• Internal concurrent transfers examples
• Hardware implementation : pinout, GPIOs configuration
• 440EPx mapping
• Programming model

CORE-CONNECT

• PLB, OPB and DCR bus features
• PLB4-to-PLB3 and PLB3-to-PLB4 bridge parameters
• PLB arbiter, OPB arbiter and PLB4-to-OPB bridge configuration
• PLB performance monitor

THE PowerPC CORE

• Pipeline
• Internal caches
• Speculative loads
• MMU

BOOK E COMPLIANT CORE

• Branch instructions
• Addressing modes
• 16-bit mac instructions
• Exception management
• Core timers
• PowerPC EABI
• JTAG debug
• Real time trace

THE FLOATING POINT UNIT

• IEEE754 basics
• Floating point load / store instructions
• Performance of multiply-accumulate instructions
• FPU exceptions

CLOCKS, RESET AND POWER MANAGEMENT

• Clocking
• Low power modes
• Reset signals
• Initialization software requirements
• IIC bootstrap controller

INTERRUPT CONTROLLER & GENERAL PURPOSE TIMERS

• Interrupt source enumeration
• Interrupt masking and acknowledgement
• Critical interrupt handlers using vectorization
• General Purpose Timers

THE DDR-SDRAM CONTROLLER

• DDR-SDRAM operation
• Differences between DDR1 and DDR2
• Jedec specification basics
• Command truth table
• Hardware interface
• ECC error correction
• Introduction to the 440EPx DDR-SDRAM controller
• Address decode
• Timing parameters programming
• Initialization routine

THE EXTERNAL BUS CONTROLLER

• External bus pinout, driver enables
• Dynamic bus sizing
• Address decoding
• Timing parameters
• Device-paced transfers
• External bus master interface
• The NAND Flash controller

THE PCI BRIDGE

• Inbound transactions handling, Outbound transactions handling
• Configuration cycles
• Setting translations between local memory space and PCI MEM space (outbound transactions), and between PCI MEM space and local memory space (inbound transactions)
• Error handling

THE 4 DMA CHANNELS

• Overview of the DMA to PLB4 and DMA to PLB3 controllers
• The buffered transfer mode
• Burst mode support
• Related signals, *DMMAck signal timing programming
• Channels bus priority
• Buffers chaining

THE GIGABIT ETHERNET CONTROLLERS

• 440EPx Ethernet controller organizatio
• PHY interface
• Frame filtering
• Ethernet controller wakeup through magic packet reception
• Buffer descriptors mechanism
• Interrupt management
• Errors management

THE SECURITY MODULE

• Introduction to encryption
• On-chip Ipsec / SSL Security acceleration engine
• Public key acceleration

THE USB INTERFACES

• Internal vs external transceiver
• USB2.0 device interface
• USB1.1 host interface
• Dedicated DMA
• UTMI bus

THE UARTS

• Transmission and reception FIFOs usage
• Flow control signals management

THE SPI PORT

• SPI protocol fundamentals
• Clock polarity and phase selection
• Transmit and receive sequences

THE IIC PORTS