Training - S12X implementation in Metrowerks environment (reference 004034A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • This training course is approved by Freescale
  • Practical exercices are built with Metrowerks compiler and Processor Expert tool
  • Metrowerks debugger is used to control code execution in both cores
   
           
    Related Trainings
   
           
    Prerequisites
  • Basic knowledge about processors
   
             
  Course Objectives
  • The course has been designed by MVD so that attendees become familiar with both the MCU itself and the Metrowerks IDE
  • Regarding on-site trainings only, we propose an extra consultancy day, during which input / output drivers will be generated
  • The course covers the hardware implementation of the S12X, particularly the connection of external memories / IOs
   
           
    Duration
  • 3-day course
   
           
    Topics

(The full description of this course can be provided on request)

INTRODUCTION TO S12X

  • S12X capabilities and target applications
  • Benefits of dual core solution and consequences for the end user
  • Simplifying the software development by using the Metrowerks IDE
  • S12X microcontrollers architecture
  • S12X derivatives
  • Compatibility with S12 MCUs
  • Modes of operation
  • Memory mapping control
  • IO pins initialization

INFRASTRUCTURE

POWER, CLOCKING AND RESET

  • Voltage regulator, power on reset circuit
  • PLL operation
  • Reset operation
  • Pierce oscillator, gain control
  • COP configuration
  • Low power modes

PORT INTEGRATION MODULE

  • External signal description
  • Memory map and register definition
  • Expanded bus pin functions

INTERNAL MEMORIES

  • EEPROM module
  • Flash modules
  • RAM module
  • Protecting memory regions against writes

EXTERNAL BUS INTERFACE

  • Selecting 3.3 or 5 V operation
  • Stretched external bus accesses
  • Data select and data direction signals
  • Normal expanded modes
  • Connecting external flash and SRAM to the S12X

DEBUGGING A MULTI-CORE SYSTEM

  • Communicating with embedded debugger through BDM
  • Enabling and activating BDM
  • Instruction tracing
  • Hardware breakpoints
  • Tagging

PROCESSOR CORES AND MULTIPROCESSOR MECHANISMS

S12 CORE

  • Programming model
  • Instruction classes
  • Detail of load / store, branch and system control assembly instructions
  • Parameterizing compiler and linker
  • Understanding sections to interface C to assembly programs

XGATE CORE

  • Programming model
  • Instruction classes
  • Detail of load / store, branch and system control assembly instructions
  • Thread execution
  • Parameterizing compiler and linker
  • Understanding sections to interface C to assembly programs

S12 AND XGATE INTERACTION MECHANISMS

  • Interrupt steering logic
  • Inter-processor interrupts
  • Accessing shared resources, semaphore management
  • Interrupt prioritization
  • Wake up from stop or wait mode

SECURITY [On demand]

  • Reprogramming the security bits
  • Complete memory erase

INTEGRATED INPUTS / OUTPUTS

As soon as driver development assistance tools will be available (Processor Expert), we will used them intensively to explain how to program peripheral operation.

TIMERS

  • Enhanced capture timers
  • Periodic Interrupt Timer
  • Pulse width modulators

ANALOG-TO-DIGITAL CONVERTER

  • External trigger pins
  • Analog circuitry
  • Digital sub-block

COMMUNICATION CONTROLLERS

  • IICV2
  • MSCANV3 controller
  • Serial Communication Interface
  • Serial Peripheral Interface

DEVELOPMENT METHODOLOGY

  • Adapting the configuration of the S12X to satisfy the end user requirements
  • Subcontracting data transfers (DMA like) to XGATE
  • Using the XGATE as a arithmetical coprocessor
  • Subcontracting the management of real time peripherals to XGATE
  • Controlling the S12 task scheduling through XGATE
   
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards.
   
           
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