• This training course is approved by Xilinx

• Learn to increase design performance and achieve repeatable results by using the PlanAhead(tm) software tool. Topics include: a product overview; synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, and block-based IP design.
  
  Note: The hands-on labs provided in this course are identical to the tutorials that are packaged with the PlanAhead software. This course is supplemented with instructor-led presentations and demos.

WHO SHOULD ATTEND ?

• Fundamentals of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE™ software flow
• Designing for Performance recommended

• Import designs into the PlanAhead software project environment
• Analyze design statistics, connectivity, and timing
• Partition and floorplan designs
• Run the Design Rule Checks (DRCs) and implement a design
• Run ExploreAhead to try multiple implementation strategies
• Import and analyze the implementation results to improve the floorplan
• Floorplan to improve performance and consistency
• Use block-based design and create and reuse module-level IP
• Employ incremental design techniques

• 2-day course

COURSE OUTLINE

Day 1

• Course Overview
• Lab 1: Getting Started with PlanAhead
• Design Analysis and Exploration
• Lab 2: Design Analysis and Exploration
• Design Partitioning and Top-Level Floorplanning
• Lab 3: Design Partitioning and Top-Level Floorplanning
• Implementing a Floorplanned Design
• Lab 4: Implementation using ExploreAhead

Day 2

• Floorplanning Techniques
• Lab 5: Floorplanning
• Tuning a Floorplan for Performance
• Lab 6: Floorplan Tuning Lab
• Block-Based Design and IP Reuse
• Lab 7: Block-Based Design and IP Reuse
• Netlist Updates and Incremental Design with PlanAhead
• Lab 8: Updating the Netlist and Incremental Design
• Floorplanning Strategies
• Course Summary

LAB DESCRIPTION

Note: All labs in this course are also available as self-guided tutorials, which are packaged with the PlanAhead software.

• Lab 1: Getting Started with PlanAhead - Illustrates the steps you take to import a synthesized design into the PlanAhead software so that you can begin floorplanning. Also introduces the PlanAhead software environment and views.
• Lab 2: Design Analysis and Exploration - Introduces the analysis features of the PlanAhead software that enable early detection of potential design issues, alternate device exploration, initial floorplanning direction, and post-implementation exploration.
• Lab 3: Design Partitioning and Top-Level Floorplanning - Introduces the concept of floorplanning. By using automated partitioning tools, you will create a top-level floorplan and experiment with sizing and shaping Pblocks based on the resources assigned to them.
• Lab 4: Implementation using ExploreAhead - Introduces the integration of the ISE software implementation tools with the PlanAhead software. Also introduces the new ExploreAhead tool for queuing multiple ISE software runs with varying strategies.
• Lab 5: Floorplanning - Describes how to analyze implementation results and to use that information for generating a floorplan aimed at increasing design performance.
• Lab 6: Floorplan Tuning - Introduces techniques to help close on timing targets consistently.
• Lab 7: Block-Based Design and IP Reuse - Describes the steps to implement a block-based methodology that includes the creation and reuse of an IP module.
• Lab 8: Updating the Netlist and Incremental Design - Illustrates the steps needed to update the project top-level netlist and to implement an incremental design change.