• Coldfire roadmap
• Differences between ColdFires and 68K processors
• 5329 block diagram, differences between 5327, 5328 and 5329
• Internal data paths
• Crossbar switch module
• Memory mapped I/O organization

V3 CORE [7-hour]

• ColdFire core versions
• Pipeline basics, V3 core pipeline : branch prediction, instruction synchronization, instruction execution time
• Practical exercice : highlighting of the execution time variation according to the prediction selected
  Programming model
• Addressing modes
• Branch instructions
• Data transfer instructions
• Arithmetic instructions
• Logic instructions
• Shift and rotate instructions
• Bit instructions
• Mac instructions
• Control instructions
• Many practical exercices contribute to understand the ColdFire assembly language
• Stack management, subroutine call and return
• C to assembly interface, organization of the stack frame
• Practical exercice : highlight of stack content evolution when a function is called
• Position dependent code vs position independent code
• Section definition
• Exception management : vector table, priority, masking
• Practical exercice : trap exception handler development
• Internal SRAM
• Cache basics : line granularity, replacement strategy, write policy, copyback buffer, information locking
  Cache operation, software control
• Practical exercice : cache flush routine
• Debug facilities : intrusive vs non-intrusive debug, BDM port, hardware breakpoints, trace port, debug interface programming model and specific instructions

HARDWARE IMPLEMENTATION [6-hour]

• Clocking, power management
• Chip configuration module
• Reset control module
• System control module
• Real Time Clock
• Flexbus, external signals, dynamic bus sizing, address decoding
• Data transfer sequence
• Burst cycles
• Timing diagrams
• External master interface
• Bus error management
• General Purpose Input / Output module
• DRAM / SDRAM basics : address multiplexing, page buffer, precharge time, refresh, FPM, EDO and SDRAM features
• SDRAM mode register initializing
• The 532X SDRAM controller : address decoding, refresh rate definition, address multiplexing selection
• Practical exercice : SDRAM controller register initializing from an SDRAM data sheet

INTERRUPT CONTROLLERS AND TIMER MODULES [2-hour]

• Vectorized vs auto-vectorized mode
• Interrupt processing sequence
• Prioritization between interrupt controllers
• Low power wake-up operation
• The software watchdog
• Edge port module
• Practical exercice : an Interrupt Service Routine has been developped to explain the external interrupts control
• PWM module, prescaler selection, polarity selection, period and duty cycle dynamic modification
• Programmable interrupt timer modules
• DMA timers

THE eDMA CONTROLLER [2-hour]

• EDMA microarchitecture
• Initialization
• Channel linking
• Hardware interface, hardware initiated transfers
• Transfer error management
• Practical exercice : data block copy using a software triggerred DMA transfer

LIQUID CRYSTAL DISPLAY CONTROLLER [2-hour]

• LCD screen format
• Graphic window on screen
• Panning
• Display data mapping
• Black-and-White operation
• Color generation
• Frame Rate modulation control
• 8 8bpp mode color STN panel

COMMUNICATION CONTROLLERS [12-hour]

• The UART Module, overview, mode of operation : UART (Wakeup, Modem), connection to the DMA controller, initialization examples
• The SSI, AC97 specification, time division multiplexing, clocking, external frame and clock operation, supported data alignment formats
• The QSPI, SPI protocol basics, master / slave operation, baud rate selection, transfer delays, command queue, transmit and receive sequences
• Practical exercice : SPI transfer in loopback mode
• The I2C controller, I2C protocol basics : addressing, multimaster operation, transfer timing diagrams, SCL and SDA pins, transmit and receive sequences
• Practical exercice : SDRAM timing parameters upload from the DIMM EEPROM
• The FlexCAN controller, CAN protocol basics, message buffers, mask registers, listen-only mode capability, receive and transmit processes, error counters
• Practical exercice : Communication with a CAN controller board plugged in a PC
• The Fast Ethernet Controller, Ethernet basics, addressing, frame format, clock recovery, MII hardware interface, auto-negociation, buffer management, buffer chaining, address filtering, use of hash tables, full duplex operation, flow control, receive and transmit sequences, error management
• Practical exercice : Communication with a PC
• The USB Host module, USB basics, EHCI specification, functional description
• The USB On-The-Go module, ULPI interface, connection of an external PHY, device data structures, device operational model, deviations from the EHCI specification
• Practical exercice : Communication with a PC

CRYPTOGRAPHY MODULES [optional]