Training - MARVELL MV64560 Implementation (reference 004408A)
 
    Prerequisites
  • Knowledge of PCI / PCI-X / PCI Express is recommended
    
           
  Course Objectives
  • The course describes the MV64560 internal data paths
  • The course explains how the host PowerPC and a CPU connected to PCI-X can synchronize to each other through the message unit
  • Operation of the PCI Express interface is detailed in Root Complex mode as well as in Endpoint mode
  • A long introduction to DDR SDRAM is done prior to describe the DDR SDRAM controller operation
  • The course focuses on the hardware implementation of the DDR SDRAM
  • The training explains how to implement chained DMA transfers, by using either IDMA channels or XOR engines
  • The course highlights the possible optimizations performance of the that can be implemented to boost the Ethernet controller
    
           
  Related courses
  • MVD provides a course on gigabit Ethernet, reference 003367A
  • MVD provides a course on PCI-X, reference 002597A
  • MVD provides a course on PCI Express, reference 003279A
  • MVD provides a course on USB2.0, reference 002606A
  • MVD provides courses on various PowerPC CPUs
   
           
    Duration
  • 4-day course
    
           
    Topics

OVERVIEW

  • 5-bus architecture, organization of a board based on MV64560
  • Frequency domains, fast path between CPU and SRAM / SDRAM
  • Internal crossbar
  • Master de-mux programming, address decode windows
  • Slave mux programming, pizza arbiters operation
  • Compatibility with MV64460

CPU INTERFACE

  • CPU address space decoding
  • Protection windows
  • Arbitration, multi-processor operation
  • CPU slave operation
  • CPU master operation (60X mode)
  • Cache coherency
  • Deadlock avoidance

DDR1/2 INTERFACE

  • Introduction to DDR SDRAM from Jedec specification
  • Differences between DDR1 and DDR2
  • DDR2 on-die terminations
  • Initialization sequence
  • DDR1/2 SDRAM controller
  • Page management
  • Transaction ordering
  • Cache coherency
  • ECC and read-modify-write transactions
  • Low power modes

DEVICE CONTROLLER

  • Functional description
  • Address and data multiplexing
  • Connecting 8/16 bit devices
  • External acknowledgement
  • Pack / unpack and burst support
  • NAND flash support, boot from NAND flash

PCI INTERFACE

  • PCI bus arbitration
  • Master operation in PCI and PCI-X mode
  • Target operation in PCI and PCI-X mode
  • PCI-to-PCI configuration transactions
  • Address decoding

PCI-EXPRESS x4 INTERFACE

  • Integrated low power SERDES PHY
  • x1, x4 link
  • Operating as either Root Complex or Endpoint
  • Link initialization
  • Arbitration and ordering
  • Messaging unit

GENERAL PURPOSE INPUT/ OUTPUT PINS

  • GPIO port, functional description
  • Interrupt request inputs
  • Multi Purpose Pin multiplexing

INTERRUPT CONTROLLERS AND TIMERS

  • Timers / counters
  • Interrupt controller functional description
  • Priority mechanism

TWSI CONTROLLER AND RESET

  • I2C protocol basics
  • TWSI controller functional description
  • Master write sequence, master read sequence
  • Slave write sequence, slave read sequence
  • Reset pins and configuration
  • Serial ROM initialization
  • Requirement for an external Central Resource CPLD

IDMA CHANNELS

  • IDMA address decoding
  • Target unit and attributes programming
  • Normal mode vs chained mode
  • Transfer descriptors, descriptor ownership
  • DMA interrupts

XOR ENGINES

  • State machine : Active, Inactive and Paused states
  • XOR operation mode
  • CRC32 operation mode
  • DMA operation mode
  • Memory Initialization operation mode
  • ECC error cleanup operation mode
  • XOR Engines interrupts

16550 COMPATIBLE UARTs

  • FIFO mode
  • Flow control
  • Transmit sequence
  • Receive sequence

USB2.0 PORTS

  • Address decoding
  • Integrated PHY
  • USB host operation, EHCI specification support
  • USB device operation, Endpoint configuration

GIGABIT ETHERNET CONTROLLERS

  • Interface to the PHY
  • SGMII support
  • Dedicated DMA
  • Transmit weighted round-robin arbitration
  • Backpressure mode
  • Transmit and receive sequences
  • Management interface
  • Synchronous FIFO interface
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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