• This training course is designed by Xilinx
• Mentor Graphics ModelSim PE is used during labs

• MVD offers a course on PCI Express protocol which can be combined with this course to cover both protocol and Xilinx Logicore

• Basic PCI and/or PCI-X protocol knowledge
• Solid knowledge of VHDL
• Solid experience with commonly used simulation tools such as Mentor Graphics ModelSim
• Basic knowledge of Xilinx ISE software

• This course focuses on the PCI Express protocol subjects that designers using the Xilinx PCI Express core should understand to complete designs faster and more easily
• An introduction to PCI Express protocol is done at the beginning to be able later to understand the operation of the back-end bus
• The course details the parameterizing of the PCI Express core
• The course targets hard and soft PCI Express cores in the Virtex-5 FPGA

• 2-day course

Day 1

• Overview
• Layers and channels
• PCI Express configuration space
• Lab1 : Exploring PCI Express configuration space
• Introduction of Xilinx PCI Express solutions
• Lab2 : Generating the Block Plus core
• Local Link interface
• Lab3 : Simulating the Block Plus core

Day 2

• TLP requests and completion packets
• Generating interrupts, legacy interrupts
• PCI Express core design considerations
• Clocking and other physical layer topics
• Lab4 : Generating the block core
• Native interface
• Lab5 : Simulating the block core
• Lab6 : Generating the Soft IP core
• PCI Express DMA design examples
• Lab7 : DMA transfer over PCI Express
• Virtex 5 PCI Express block, clocking concerns
• PCI Express core bandwidth calculation
• Completion streaming for higher bandwidth explained