| |
| Training - i.MX31implementation +
LTIB (reference 004632A) |
|
| |
| |
|
 |
|
Partners
- Do not hesitate to request the detailed
course description by contacting training@mvd-fpga.com
- This course is approved by Freescale
- Practical labs are based on the
i.MX31 evaluation board
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Related courses
MVD offers the following related courses
- ARM1136 (Only an overview of this core is
included in this course )
- USB,
reference 002606A
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Practical labs
- For on-site courses, labs can be run
under 2 possible environments :
- GNU/Lauterbach or
- GNU/BDI2000
- For open courses, labs are run under GNU/Lauterbach
environment
|
|
|
| |
|
|
|
|
|
|
| |
|
 |
|
Prerequisites
- Experience of a processor or DSP is
recommended
- Knowledge of Linux basics is recommended
|
|
|
| |
|
|
|
|
|
|
 |
|
 |
|
Course Objectives
- The course details the hardware
implementation of the i.MX31
microcontroller
- The boot sequence and the
clocking are explained
- The course explains all
parameters that affect the performance of
the system in order to easily perform the
final tuning
- A description of all internal
peripherals is provided
- An overview of the ARM1136 core
helps to understand issues caused by
cache and MMU
- The course ends with practical
labs explaining how to generate a Linux
image as well as a Root File System, by
using a tool called LTIB [Linux Target
Image Builder]
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Duration
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Topics (The full description of this
course can be provided on request)
ARCHITECTURE OF i.MX31
- Clarifying the internal data paths : AHB
bus, peripheral buses
- Highlighting the purpose of the 2 central
interconnect units : MAX and M3IF
- Organization of a board based on i.MX31
THE ARM1136JF-S CORE
- Presentation of the core, architecture
and programming model
- Operating modes : user, system, super,
IRQ, FIQ, undef and abort
- ARM vs Thumb instruction sets,
interworking
- Branch instructions, implementation of C
call and return statements
- Level1 cache operation
- Memory management unit
- C-to-Assembly interface
- Exception mechanism, handler table
- Debug facilities
RESET AND CLOCKING
- Clock distribution
- PLL output frequency calculation
- Power-up sequence
- Low power modes, clock gating
- Global reset vs warm reset
- System boot mode selection
SYSTEM CONTROL
- GPIO module
- General Purpose Input interrupt request
capability
- Signal description
THE ARM11 PLATFORM
- MAX parameterizing
- ARM Vector Interrupt Controller
- Level 2 cache operation
SMART DMA CONTROLLER
- Scheduler
- CRC calculation unit
- SDMA initialisation
- Instruction description
ACCESSING EXTERNAL MEMORIES
- Description of the Master Arbitration and
Buffering [MAB] unit
- Description of the M3IF arbitration [M3A]
- Introduction to DDR SDRAM
- Enhanced DDR SDRAM controller
- NAND flash controller, boot from flash
STANDARD PARALLEL INTERFACES
VIDEO PROCESSING UNITS
- Video acquisition
- MPEG4 encoder
- Image Processing Unit
- Graphics accelerator
AUDIO RELATED INTERFACES
- SSI interfaces
- Digital audio multiplexor
COMMUNICATION CONTROLLERS
- 1-wire interface
- Configurable SPI
- I2C interfaces
- UART
- USB
GENERATING THE LINUX KERNEL IMAGE
- Introducing the tools required to
generate the kernel image
- What is required on the host before
installing LTIB
- Common package selection screen
- Common target system configuration screen
- Building a complete BSP with the default
configurations
- Creating a Root Filesystems image
- Re-configuring the kernel under LTIB
- Selecting user-space packages
- Setup the bootloader arguments to use the
exported RFS
- Debugging Uboot and the kernel by using
Trace32
- Command line options
- Adding a new package
- Other deployment methods
- Creating a new package and integrating it
into LTIB
- A lot of labs have been created to
explain the usage of LTIB
|
|
|
 |
|
|
|
|
|
|
| |
|
 |
|
Documentation
Training manuals will be given to participants
during training. Precise and easy of use, those
notes can be used as a reference afterwards. |
|
|
 |
|
|
|
|
|
|