• Introduction to e600 pipeline
• e600 pipeline implementation
• Issue queue resource requirements
• Execution model
• Dispatch conditions, completion conditions
• Execution serialization
• Branch management
• Guarded memory

INTERNAL DATA FLOWS

• L1 and L2 cache loading, hit under miss
• The MSS [Memory Sub System]
• The load fold queue
• The store miss merging mechanism
• The BIU [Bus Interface Unit]
• Purpose of sync and eieio instructions

L1 AND L2 CACHES

• Cache basics
• Cache related page / block attributes
• e600 L1 cache
• Transient load instructions benefits
• L2 cache organization
• Cache coherency basics
• The MESI L1 data line states
• MESI snooping sequences involving the e600 and a PCI Express master
• Cache related instructions

e600 PROGRAMMING

• User and supervisor registers
• Branch instructions
• The system call communication path between applications and RTOS
• Integer load / store instructions, boolean semaphore management
• Integer arithmetic and logic instructions
• IEEE754 basics
• FPU operation
• The EABI
• Code and data sections, small data areas benefits

ALTIVEC

• Altivec introduction, SIMD processing
• Intra vs inter element instructions
• ANSI C extension to support vector operators
• Vector load / store instructions
• Vector integer instructions
• Vector float instructions
• Vector permut instructions
• Data streams management
• EABI extension to support Altivec

THE MEMORY MANAGEMENT UNIT

• MMU goals
• The PowerPC address processing
• 32-bit or 36-bit real address size selection
• WIMG attributes definition
• Process protection through VSID selection
• TLB organization
• Page translation
• Software vs hardware TLB reload
• MMU implementation in real-time sensitive applications

THE EXCEPTION MECHANISM

• Platform clock
• Power-on reset sequence
• Boot page translation
• Power management

MPX COHERENCY MODULE

• I/O arbiter
• Transaction queue
• Global data multiplexor

PROGRAMMABLE INTERRUPT CONTROLLER

• Open PIC architecture compatibility
• Interrupt nesting
• Description of the 4 timers / counters
• Message interrupts

DDR-SDRAM MEMORY CONTROLLER

• DDR2 operation
• Jedec specification basics
• Hardware interface
• Bank activation
• ECC error correction
• On-die termination and driver calibration
• Introduction to the DDR-SDRAM controller
• Address decode
• Timing parameters programming
• Initialization routine

ENHANCED LOCAL BUS CONTROLLER

• Multiplexed or non-multiplexed address and data buses
• Burst support
• GPCM, UPMs states machines
• Interfacing to ZBT SRAMs
• Interfacing to DSP host ports
• NAND flash controller

INTEGRATED DMA CONTROLLER

• Priority between the 4 channels
• Support for cascading descriptor chains
• Scatter / gathering
• Ability to start DMA from external 3-pin interface

PCI INTERFACE

• Bridge features
• Inbound transactions handling, Outbound transactions handling
• PCI-to-memory and memory-to-PCI streaming
• Host vs agent configuration

PCI EXPRESS INTRFACE

• Modes of operation, Root Complex / Endpoint
• Byte swapping
• Transaction ordering rules
• Programming inbound and outbound ATMUs

PERFORMANCE MONITOR AND DEBUG FEATURES

• Display interfaces
• Display color depth
• Plane blending
• Utilization of area descriptor
• Moving images through the dedicated DMA channel

I2C CONTROLLERS

• I2C protocol fundamentals
• Transfer timing diagrams, SCL and SDA pins
• Transmit and receive sequence

SERIAL INTERFACE

• Introduction to UART protocol
• Description of the NS16552 compliant Uarts
• Flow control signal management

SPI

• SPI protocol fundamentals
• Transmit sequence
• Receive sequence

SYNCHRONOUS SERIAL CONTROLLER