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| Training - ARM1176 system design
(reference 003772A) |
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Partners
- Do not hesitate to request the detailed
course description by contacting training@mvd-fpga.com
- This training course is approved by ARM
- This training does not cover the
description of ARM development tools : it
is possible to mix ARM7/9 system design
and ARM1176 system design to form a 5-day
course including 1-day on embedded
software design
- On-site only course
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Practical labs
- For on-site
courses, labs can be run under 3 possible
environments :
- CodeWarrior/ADS/AXD
- Eclipse/RVDS
- GNU/Lauterbach
simulator
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Prerequisites
- A basic awareness
of the ARM is highly recommended
especially the knowledge of ARM V4T and
V5TE instruction sets
- A basic
understanding of assembler or C
programming would be useful but not
essential
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Course Objectives
- This course takes
an in depth look at the considerations
you will need to take into account when
designing a system containing an ARM1136
- It is aimed
at :
- Software
engineers who not only want to
obtain details of how to write
software to run on the ARM11, but
also wish to obtain an
understanding of hardware design
issues
- Hardware
engineers who need to understand
how to design ARM11 based
systems, but also wish to obtain
an understanding of the issues of
writing software to run on that
system
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Duration
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Topics (The full description of this course
can be provided on request)
First day
THE ARM ARCHITECTURE
- ARM operation modes
- The ARM registers set
- Program Status Registers
- Exception handling, vector table,
automatic switch into ARM mode
- Instruction sets : ARM branches and
subroutines
ARM11 CPU ARCHITECTURE
- ARM11 superscalar pipeline operation
- Dynamic vs static branch prediction
- Out of order execution
- Return stack
MEMORY SUBSYSTEMS
- Cache basics
- Hit under miss and its consequence : out
of order abort
- ARM11 related instructions
- Highlighting data flows between main
memory, L1 cache and L2 cache
- Tightly coupled memories
- Configuration & control through CP15
Second day
MEMORY MANAGEMENT & PROTECTION
- Introduction to page management
- V6 virtual memory architecture
- ARM V6 endianness
- Data alignment
ARMv6 INSTRUCTION SET
- Additional classes of instruction
- Standard multiply extension
- Long multiplication
- Packed data types
- V6z NOP32 instruction to enter low power
mode
PRIMECELL VECTORED INTERRUPT CONTROLLER
- Interrupt controllers
- Primecell VICs
- Reducing interrupt latency through
automatic vector generation
- VIC basic signal timing
- Interrupt priority and masking
Third day
AHB PROTOCOL
- Transfers with AHB
- Use of HREADY, HRESP & HTRANS signals
- Implementation of indivisible
transactions
APB
- Address decoding stages
- APB interconnect
- APB in AMBA3
ARM11 DEBUG
- Basic debug requirements
- Embedded core debug
- DBGTAP interfacing
TRACING AN ARM11-BASED SYSTEM
- Motivation to real-time trace
- About core sight ETM11
- Tracing with core sight ETM11
- Implementing trace : ETB
Fourth day
ARM1136 OVERVIEW
- Block diagram
- New features compared to ARM9
- The four external bus interfaces
- DMA between L1 TCMs and L2 memory system
- Low interrupt latency mode through VIC
dedicated vector port
- Implementation flow overview, simulations
models
- ARM1136 example system
- Reset and clocking
- Booting an ARM1136
LEVEL ONE AND LEVEL TWO MEMORY SYSTEMS
- TCM and cache interaction
- DMA channel
- Endianness
- Peripheral interface transfers
- AHB ports
- Implementation of the L210 level-2 cache
controller
ARM11 MULTI-PROCESSOR SYNCHRONISATION
- Introduction to semaphore
- Using the SWP instruction
- Using ARMv6 synchronisation instructions
: LDREX, STREX and CLREX
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Documentation
Training manuals will be given to participants
during training. Precise and easy of use, those
notes can be used as a reference afterwards. |
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