MPC55XX OVERVIEW

• Automotive MPC55XX roadmap
• Internal architecture
• Functional pin multiplexing
• Physical characteristics
• Memory map, internal register space

e200 CORE

• Differences between the new Book E architecture and the classic PowerPC architecture
• The instruction pipeline
• Integer and floating point execution units
• SPE instruction set, signal processing capability, new data types
• Vector and scalar floating point
• Mapping instructions to C level intrinsics
• Execution timing
• The MMU, 32-entry fully associative TLB, page size selection
• Hardware assist for TLB miss exception
• Page attributes WIMGE
• Process protection, variable number of PID registers and sharing
• TLB initialization
• The 32-kB unified L1 cache, pseudo round-robin replacement algorithm, 8-way set associativity
• Cache lookup flow
• 8-entry store buffer
• Cache initialisation, flush and invalidation methods
• Cache-related instructions
• ABI : sections, C-to-assembly interface
• Book E exception handling, critical versus non critical, handler table, syndrome registers updating when an exception is taken, specific machine check interrupt, exception nesting, recoverability from interrupt, soft stop
• Exception handler steps
• Core timers : Dec, TB, FIT and Software Watchdog
• Power management, disabling the timer, interrupts and power management
• Nexus emulation, real time trace when the e200 core executes cached instructions
• Watchpoint logic, triggering capabilities based on user programmable events

THE INTERRUPT CONTROLLER

• Up to 504 on-chip module interrupt sources
• Software vs hardware vector mode
• Hardware acceleration for ISRs : use of 9-bit vectors
• Preemption, priority management
• Software interrupts
• External IRQs

HARDWARE IMPLEMENTATION

• FMPLL
• Configuration pins
• Reset configuration halfword
• Boot assist module, 4 different boot modes
• MMU configuration after BAM executes
• Initialization sequence
• GPIO configuration
• External bus interface, pinout
• Memory controller with support for SDR flash and SRAM
• Dynamic bus sizing
• Compatibility with the external bus of the MPC5XX
• Support for external master accesses to internal addresses
• Burst support
• Chip-select programming

ON-CHIP MEMORIES

• 2 MB on-chip flash
• Integrated ECC
• Censorship protection
• Read while write operation
• Erase and program sequences
• 111 kB on-chip SRAM : general purpose SRAM, cache and eTPU RAMs

eDMA AND CROSSBAR

• Autonomous IO control
• Parallel memory bus architecture, concurrent accesses
• Programmable master priorities on a per-slave basis
• 64 independent channels with link capability
• Parking on slave ports
• eDMA sources
• Transfer control descriptors, inner and outer loops, modulo feature
• Scatter / gather feature
• DMA channel arbitration
• DMA error reporting

THE eTPUs

• Real time hardware events processing, scheduling, priority scheme
• Microengine operation
• New arithmetic, logical and control instructions
• Angle clock hardware
• DMA support
• Dual eTPU shared resources
• Introduction to the eTPU functions QOM, NITC, PWM, SIOP, UART
• Interchannel communication
• Channel service max latency time calculation
• eTPU development tools, Ashware debugger

eMIOS

• Introduction to time functions supported by the 24 unified channels
• DMA request per channel
• Pin serialization / deserialization
• eMIOS interrupt requests
• Double action submodules
• PWM submodules, center aligned PWM
• Windowed programmable time accumulation
• Quadrature decode

eQADC

• Analog inputs multiplexing
• 12-bit AD resolution
• Queue management, trigger sources
• Conversion queue priority scheme
• Conversion cycle times
• eQADC command / data flow
• Hardware interface
• ADC error correction

DSPI

• SPI protocol explanation, master / slave operation
• Command queue
• Flexible programming transfer attributes on a per-frame basis
• Transmit and receive sequences
• DMA configuration

eSCI

• UART basics
• Double buffering
• Wake up mode
• Transmit and receive sequences
• Support for LIN master operation
• DMA request line

The FlexCAN controllers

• CAN protocol basics
• Message buffer structure
• Mask registers
• Listen-only mode capability
• Receive and Transmit processes
• Error counters

THE FAST ETHERNET CONTROLLER

• Overview
• MII pinout
• Buffer descriptor description
• Initialization sequence
• Error management
• Interrupts

THE FLEXRAY CONTROLLER